scholarly journals Efficient Implementation of Multichannel FM and T-DMB Repeater in FPGA with Automatic Gain Controller

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 482
Author(s):  
Mangi Han ◽  
Youngmin Kim
Keyword(s):  
High Performance ◽  
Electronic Device ◽  
Finite Impulse Response ◽  
Parallel Implementation ◽  
Power Level ◽  
Digital Signal ◽  
Digital Circuit ◽  
Output Power Level ◽  
Verilog Hdl ◽  
Field Programmable

In this study, we implemented a high-performance multichannel repeater, both for FM and T-Digital Multimedia Broadcasting (DMB) signals using a Field Programmable Gate Array (FPGA). In a system for providing services using wireless communication, a radio-shaded area is inevitably generated due to various obstacles. Thus, an electronic device that receives weak or low-level signals and retransmits them at a higher level is crucial. In addition, parallel implementation of digital filters and gain controllers is necessary for a multichannel repeater. When power level is too low or too high, the repeater is required to compensate the power level and ensure a stable signal. However, analog- and software-based repeaters are expensive and they are difficult to install. They also cannot effectively process multichannel in parallel. The proposed system exploits various digital signal-processing algorithms, which include modulation, demodulation, Cascaded Integrator Comb (CIC) filters, Finite Impulse Response (FIR) filters, Interpolated Second Ordered Polynomials (ISOP) filters, and Automatic Gain Controllers (AGCs). The newly proposed AGC is more efficient than others in terms of computation amount and throughput. The designed digital circuit was implemented by using Verilog HDL, and tested using a Xilinx Kintex 7 device. As a result, the proposed repeater can simultaneously handle 40 FM channels and 6 DMB channels in parallel. Output power level is also always maintained by the AGC.

scholarly journals VLSI Design and Implementation for Adaptive Filter using LMS Algorithm

2012 ◽  
pp. 297-301
Author(s):  
Asit Kumar Subudhi ◽  
Biswajit Mishra ◽  
Mihir N. Mohanty
Keyword(s):  
High Performance ◽  
Adaptive Filters ◽  
Finite Impulse Response ◽  
Vlsi Design ◽  
Digital Signal ◽  
Fir Filter ◽  
Lms Algorithm ◽  
Least Mean Square ◽  
Field Programmable ◽  
Adaptive Noise

Adaptive filters, as part of digital signal systems, have been widely used, as well as in applications such as adaptive noise cancellation, adaptive beam forming, channel equalization, and system identification. However, its implementation takes a great deal and becomes a very important field in digital system world. When FPGA (Field Programmable Logic Array) grows in area and provides a lot of facilities to the designers, it becomes an important competitor in the signal processing market. In general FIR structure has been used more successfully than IIR structure in adaptive filters. However, when the adaptive FIR filter was made this required appropriate algorithm to update the filter’s coefficients. The algorithm used to update the filter coefficient is the Least Mean Square (LMS) algorithm which is known for its simplification, low computational complexity, and better performance in different running environments. When compared to other algorithms used for implementing adaptive filters the LMS algorithm is seen to perform very well in terms of the number of iterations required for convergence. This phenomenon can be achieved by a sufficient choice of bit length to represent the filter’s coefficients. This paper presents a lowcost and high performance programmable digital finite impulse response (FIR) filter. It follows the adaptive algorithm used for the development of the system. The architecture employs the computation sharing algorithm to reduce the computation complexity.

scholarly journals Embedded GPU Implementation for High-Performance Ultrasound Imaging

Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 884
Author(s):  
Stefano Rossi ◽  
Enrico Boni
Keyword(s):  
High Performance ◽  
Graphics Processing Unit ◽  
Digital Signal ◽  
Processing Unit ◽  
Embedded Computing ◽  
Field Programmable ◽  
Peripheral Component Interconnect ◽  
Programmable Gate Arrays ◽  
Graphics Processing ◽  
Signal Processors

Methods of increasing complexity are currently being proposed for ultrasound (US) echographic signal processing. Graphics Processing Unit (GPU) resources allowing massive exploitation of parallel computing are ideal candidates for these tasks. Many high-performance US instruments, including open scanners like ULA-OP 256, have an architecture based only on Field-Programmable Gate Arrays (FPGAs) and/or Digital Signal Processors (DSPs). This paper proposes the implementation of the embedded NVIDIA Jetson Xavier AGX module on board ULA-OP 256. The system architecture was revised to allow the introduction of a new Peripheral Component Interconnect Express (PCIe) communication channel, while maintaining backward compatibility with all other embedded computing resources already on board. Moreover, the Input/Output (I/O) peripherals of the module make the ultrasound system independent, freeing the user from the need to use an external controlling PC.

scholarly journals Design and Implementation of Compressor based 32-bit Multipliers for MAC Architecture

2019 ◽  
Vol 8 (9) ◽  
pp. 2007-2014
Keyword(s):  
Circuit Design ◽  
High Performance ◽  
Arithmetic Operation ◽  
Digital Signal ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Digital Circuit Design ◽  
Unit Design ◽  
High Performance Systems ◽  
Signal Processors

Arithmetic operations play a major role in digital circuit design like adders, multipliers etc. Multiplication is an important fundamental arithmetic operation in high performance systems such as microprocessor and digital signal processors circuits. Implementation of multipliers using compressor circuit over conventional adders will reduce the number of levels of addition, which will in turn reduces the latency of the multiplier. Multiplier module is most likely the essential part of MAC (Multiplier-Accumulator) unit design. Compressor based multipliers in MAC architecture design results high performance. FPGA and ASIC implementations of 4:2 compressor based 32-bit Wallace and Dadda multipliers can be done by using Xilinx Vivado and Cadence CMOS technology tools. These results are compared with other multiplier designs with respect to area, latency and power dissipation.

scholarly journals An Efficient MAC Architecture using Multiplier for DSP and DIP Operations

2018 ◽  
Vol 7 (2.16) ◽  
pp. 110
Author(s):  
P Rahul Reddy ◽  
Pandya Vyomal N ◽  
Abhishek Choubey
Keyword(s):  
Signal Processing ◽  
Hearing Aids ◽  
High Performance ◽  
Digital Signal ◽  
Building Blocks ◽  
Hardware Architecture ◽  
Verilog Hdl ◽  
Medical Discipline ◽  
Critical Components ◽  
Wallace Tree Multiplier

DSP operations are very important part of engineering as well as medical discipline. For the designing of DSP operations Multiplication is play important role to perform signal processing operations. Multiplier is one of the critical components in the area of digital signal processing and hearing aids. So the objective is to design an efficient MAC hardware architecture using multiplier with assistance of compressors by conserving less area, power and delay. In this paper, efficient hardware architecture of MAC using a modified Wallace tree multiplier is proposed. The proposed MAC uses multiplier with novel compressor designs and adders as primitive building blocks for efficient application. Further, the Verilog-HDL coding of 8 bit MAC architecture and their FPGA implementation by Xilinx ISE 14.4 Synthesis Tool on Virtex7 kit have been done. The proposed compressor and adder based architecture used to be applied to MAC unit and in comparison to the previous design MAC unit and verified that the proposed architecture have reduce in terms of area, delay and power. The high performance is obtained by using a new hierarchical structure, these adders are called compressors.  These compressors make the multipliers faster as compared to the conventional design used in Engineering, Science & Technology as well as medical discipline.

scholarly journals DESIGN OF HIGH PERFORMANCE MULTIPLIERLESS LINEAR PHASE FINITE IMPULSE RESPONSE FILTERS

2017 ◽  
Vol 10 (13) ◽  
pp. 66
Author(s):  
A Aparna ◽  
T Vigneswaran
Keyword(s):  
Low Power ◽  
Impulse Response ◽  
High Speed ◽  
High Performance ◽  
Finite Impulse Response ◽  
Research Work ◽  
Digital Signal ◽  
Fir Filter ◽  
Pass Filter ◽  
Finite Impulse Response Filters

This research work proposes the finite impulse response (FIR) filters design using distributed arithmetic architecture optimized for field programmable gate array. To implement computationally efficient, low power, high-speed FIR filter a two-dimensional fully pipelined structure is used. The FIR filter is dynamically reconfigured to realize low pass and high pass filter by changing the filter coefficients. The FIR filter is most fundamental components in digital signal processing for high-speed application. The aim of this research work is to design multiplier-less FIR filter for the requirements of low power and high speed various embedded applications. 

scholarly journals Design and Implementation of Hybrid FIR Filters using Vedic Multiplier and Fast Adders

2019 ◽  
Vol 8 (4) ◽  
pp. 11849-11853
Keyword(s):  
High Speed ◽  
High Performance ◽  
Noise Suppression ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Fir Filter ◽  
Vital Role ◽  
Finite Impulse Response Filters ◽  
Vedic Multiplier ◽  
Impulse Response Filters

FIR (Finite Impulse Response) filters play a significant role in the field of Digital Signal Processing (DSP) to eliminate noise suppression in Electro Cardio Graph (ECG), Imaging devices and the signal stored in analog media. So filter evaluation is accomplished to reduce the noise level. The Filter passes only the desired frequency to pass thereby reducing distortion in the processed signal during measurement. The FIR filter comprises of basic units like adders, multipliers and the delay element for its operations.FIR and IIR are the two types of digital filters chosen based on the range of inputs, complexity and size requirement. Multipliers and adders play a vital role in deterring the performance of FIR filter. In this work, we design and analyze different multiplier and adder for high-performance Fir filter implementation. The Vedic Mathematics is the methods containing 16 Sutras to aid fast mental calculations. In this work, we propose modified Anurupye Vedic multiplier methods with Kogge Stone fast adder for implementation in the direct form FIR filter. This approach provides 1.5% decrease in delay and 10.2% reduced in power, hence increasing speed marginally than previous methods. Along with low power consumption in Very High-Speed Hardware Description Language (VHDL), all the adders and the multiplier topologies are Synthesized using (Xilinx Spartan – 6 FPGA) Trainer Kit and the proposed 8 – Tap FIR filter is executed using this Board

High-Performance Computing Using FPGAs for Improving the DTC Performances of Induction Motors

2020 ◽  
pp. 133-153
Author(s):  
Saber Krim ◽  
Mohamed Faouzi Mimouni
Keyword(s):  
Digital Signal Processor ◽  
High Performance ◽  
Induction Motors ◽  
Control Method ◽  
Direct Torque Control ◽  
Digital Signal ◽  
Sampling Frequency ◽  
Torque Control ◽  
Field Programmable ◽  
Torque Ripples

The conventional direct torque control (DTC) of induction motors has become the most used control strategy. This control method is known by its simplicity, fast torque response, and its lack of dependence on machine parameters. Despite the cited advantages, the conventional DTC suffers from several limitations, like the torque ripples. This chapter aims to improve the conventional DTC performances by keeping its advantages. These ripples depend on the hysteresis bandwidth of the torque and the sampling frequency. The conventional DTC limitations can be prevented by increasing the sampling frequency. Nevertheless, the operation with higher sampling frequency is not possible with the software solutions, like the digital signal processor (DSP), due to the serial processing of the implemented algorithm. To overcome the DSP limitations, the field programmable gate array (FPGA) can be chosen as an alternative solution to implement the DTC algorithm with shorter execution time. In this chapter, the FPGA is chosen thanks to its parallel processing.

Dynamic Partial Reconfiguration with FIR Filter Application

2015 ◽  
Vol 4 (3) ◽  
pp. 201
Author(s):  
Noopur Astik
Keyword(s):  
Finite Impulse Response ◽  
Digital Signal ◽  
Fir Filter ◽  
Partial Reconfiguration ◽  
Dynamic Partial Reconfiguration ◽  
Pass Filter ◽  
Direct Form ◽  
Field Programmable ◽  
Low Pass ◽  
High Pass

Dynamic partial reconfiguration has evolved as a very prominent state of art for efficient area utilization of <em>Field Programmable Gate Array</em> (FPGA) as well as significant reduction in its overall power consumption when properly used to lessen the idle logic on FPGA. It provides desired results even as the computational complexity increases in the field of Digital Signal Processing. This paper explains Dynamic Partial Reconfiguration (DPR) with an example of Finite Impulse response (FIR) filter of order 10. Initially RTL coding for Direct Form FIR structure is written in Verilog in fixed point format for low pass and high pass filter modules using ISE Design suite. Functioning of the both the modules is verified individually through hardware co-simulation on ZYBO (Zynq Board) from Digilent using Black Box from System Generator. Finally dynamic partial reconfigurable FIR filter with low pass and high pass as reconfigurable modules is implemented on ZYBO using PlanAhead tool. Final comparison of resource utilization with and without DPR is presented

Low Power High Performance Full Adder Design Using Gate Diffusion Input Techniques

2020 ◽  
Vol 17 (4) ◽  
pp. 1595-1599
Author(s):  
N. Suresh ◽  
K. Subba Rao ◽  
R. Vassoudevan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Large Scale ◽  
Digital Signal ◽  
Full Adder ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Essential Components

Very Large Scale Integrated (VLSI) technology for a widespread use of high performance portable integrated circuit (IC) devices such as MP3, PDA, mobile phones is increasing rapidly. Most of the VLSI applications, such as digital signal processing, image processing and microprocessors, extensively use arithmetic operations. In this research novel low power full adder architecture has been proposed for various applications which uses the advanced adder and multiplier designs. A full-adder is one of the essential components in digital circuit design; many improvements have been made to reduce the architecture of a full adder. In this research modified full adder using GDI technique is proposed to achieve low power consumption. By using GDI cell, the transistor count is greatly reduced, thereby reducing the power consumption and propagation delay while maintaining the low complexity of the logic design. The parameters in terms of Power, Delay, and Surface area are investigated by comparison of the proposed GDI technology with an optimized 90 nm CMOS technology.

Design and implementation of pervasive DA based FIR filter and feeder register based multiplier for software definedradio networks

2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Mohan Kumar ◽  
Ranga Raju
Keyword(s):  
Energy Efficiency ◽  
Impulse Response ◽  
Power Dissipation ◽  
Software Defined Radio ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Fir Filter ◽  
Infinite Impulse Response ◽  
Content Type ◽  
Field Programmable

Purpose Digital signal processing (DSP) applications such as finite impulse response (FIR) filter, infinite impulse response and wavelet transformation functions are mainly constructed using multipliers and adders. The performance of any digital applications is dependent on larger size multipliers, area and power dissipation. To optimize power and area, an efficient zero product and feeder register-based multiplier (ZP and FRBM) is proposed. Another challenging task in multipliers is summation of partial products (PP), results in more delay. To address this issue, the modified parallel prefix adder (PPA) is incorporated in multiplier design. In this work, different methods are studied and analyzed for designing FIR filter, optimized with respect to area, power dissipation, speed, throughput, latency and hardware utilization. Design/methodology/approach The distributed arithmetic (DA)-based reconfigurable FIR design is found to be suitable filter for software-defined radio (SDR) applications. The performance of adder and multipliers in DA-FIR filter restricts the area and power dissipation due to their complexity in terms of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by using PPA which is based on Ling equation. The MDA-RFIR filter is designed for higher filter length (N), i.e. N = 64 with 64 taps and this design is developed using Verilog hardware description language (HDL) and implemented on field-programmable gate array. The design is validated for SDR channel equalizer; both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of part name XC7A100tCSG324. Findings The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency. The theoretical and practical comparisons have been done, and the practically obtained results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed product and energy efficiency are better about 3.5 times, 31, 45 and 29%, respectively. Originality/value The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency.

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