STATISTICAL MODELING FOR LEARNING VECTOR QUANTIZER CODEBOOK DESIGN IN THE WAVELET DOMAIN

2010 ◽  
Vol 07 (01) ◽  
pp. 41-50
Author(s):  
P. AROCKIA JANSI RANI ◽  
V. SADASIVAM
Keyword(s):  
High Performance ◽  
Statistical Approach ◽  
Input Image ◽  
Wavelet Domain ◽  
Coding Efficiency ◽  
Codebook Design ◽  
Vector Quantizer ◽  
Effective Manner ◽  
Energy Compaction ◽  
New Framework

A statistical approach for modeling the code vectors designed using a supervised learning neural network is proposed in this paper. Since wavelet-based compression is more robust under transmission and decoding errors, the proposed work is implemented in the wavelet domain. Two crucial issues in compression methods are the coding efficiency and the psycho visual quality achieved while modeling different image regions. In this paper, a high performance wavelet coder which provides a new framework for handling these issues in a simple and effective manner is proposed. First the input image is subjected to wavelet transform. Then the transformed coefficients are subjected to Quantization followed by the well known Huffman Encoder. In the Quantization process, initially a codebook is designed using Learning Vector Quantizer. Since codebook is an essential component for the reconstructed image quality and also to exploit the spatial energy compaction of the codevectors, the codebook is further modeled using Savitzky–Golay polynomial. Experimental results show that the proposed work gives better results in terms of PSNR that are competitive with the state-of-art coders in literature.

High Performance Working Practices: The New Framework for Nurturing Sustainability?

2011 ◽  
Author(s):  
Ana Martins ◽  
Kevin Brown ◽  
Orlando Pereira ◽  
Isabel Martins
Keyword(s):  
High Performance ◽  
Working Practices ◽  
New Framework

scholarly journals An Adversarial Attacks Resistance-based Approach to Emotion Recognition from Images using Facial Landmarks

2021 ◽  
Author(s):  
Harisu Abdullahi Shehu ◽  
William Browne ◽  
Hedwig Eisenbarth
Keyword(s):  
Emotion Recognition ◽  
High Performance ◽  
Input Image ◽  
Large Decrease ◽  
Facial Landmarks ◽  
The Past ◽  
Homogeneous Representation ◽  
Small Change ◽  
Deep Learning Model ◽  
Representation Of Knowledge

Emotion recognition has become an increasingly important area of research due to the increasing number of CCTV cameras in the past few years. Deep network-based methods have made impressive progress in performing emotion recognition-based tasks, achieving high performance on many datasets and their related competitions such as the ImageNet challenge. However, deep networks are vulnerable to adversarial attacks. Due to their homogeneous representation of knowledge across all images, a small change to the input image made by an adversary might result in a large decrease in the accuracy of the algorithm. By detecting heterogeneous facial landmarks using the machine learning library Dlib we hypothesize we can build robustness to adversarial attacks. The residual neural network (ResNet) model has been used as an example of a deep learning model. While the accuracy achieved by ResNet showed a decrease of up to 22%, our proposed approach has shown strong resistance to an attack and showed only a little (< 0.3%) or no decrease when the attack is launched on the data. Furthermore, the proposed approach has shown considerably less execution time compared to the ResNet model.

Cost Effective and High Performance 28nm FPGA with New Disruptive Silicon-Less Interconnect Technology (SLIT)

2014 ◽  
Vol 2014 (1) ◽  
pp. 000599-000605 ◽  
Author(s):  
Woon-Seong Kwon ◽  
Suresh Ramalingam ◽  
Xin Wu ◽  
Liam Madden ◽  
C. Y. Huang ◽  
...  
Keyword(s):  
High Performance ◽  
Process Integration ◽  
Cost Effective ◽  
Disruptive Innovation ◽  
Design Rule ◽  
Wind Condition ◽  
Silicon Etching ◽  
Wafer Level ◽  
Effective Manner ◽  
Interconnect Technology

This paper introduces the first comprehensive demonstration of new disruptive innovation technology comprising multiple Xilinx patent-pending innovations for highly cost effective and high performance Xilinx FPGA, which is so called stack silicon-less interconnect technology (SLIT) that provides the equivalent high-bandwidth connectivity and routing design-rule as stack silicon interconnect (SSI) technology at a cost-effective manner. We have successfully demonstrated the overall process integration and functions of our new SLIT-employed package using Virtex® -7 2000T FPGA product. Chip-to-Wafer stacking, wafer level flux cleaning, micro-bump underfilling, mold encapsulation are newly developed. Of all technology elements, both full silicon etching with high etch selectivity to dielectric/fast etch rate and wafer warpage management after full silicon etching are most crucial elements to realize the SLIT technology. In order to manage the wafer warpage after full Si removal, a couple of knobs are identified and employed such as top reinforcement layer, micro-bump underfill properties tuning, die thickness/die-to-die space/total thickness adjustments. It's also discussed in the paper how the wafer warpage behaves and how the wafer warpge is managed. New SLIT module shows excellent warpage characteristics of only −30 μm ~ −40 μm at room temperature for 25 mm × 31 mm in size and +20 μm ~ +25 μm at reflow temperature. Thermal simulation results shows that thermal resistance of new SLIT package is almost comparable to that of standard 2000T FCBGA package using TSV interposer with standard heat sink configuration and air wind condition. The reliability assessment is now under the study.

New Stacked Die Interconnect Technology for High-Performance and Low-Cost FPGA

2015 ◽  
Vol 12 (3) ◽  
pp. 111-117
Author(s):  
Woon-Seong Kwon ◽  
Suresh Ramalingam ◽  
Xin Wu ◽  
Liam Madden ◽  
C. Y. Huang ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Process Integration ◽  
Cost Effective ◽  
Design Rule ◽  
Innovative Technology ◽  
Wind Condition ◽  
Wafer Level ◽  
Effective Manner ◽  
Interconnect Technology

This article introduces the first comprehensive demonstration of new innovative technology comprising multiple key technologies for highly cost-effective and high-performance Xilinx field programmable gate array (FPGA), which is so-called stack silicon-less interconnect technology (SLIT) that provides the equivalent high-bandwidth connectivity and routing design-rule as stack silicon interconnect (SSI) technology at a cost-effective manner. We have successfully demonstrated the overall process integration and functions of our new SLIT-employed package using Virtex®-7 2000T FPGA product with chip-to-wafer stacking, wafer-level flux cleaning, microbump underfilling, mold encapsulation, and backside silicon removal. Of all technology elements, both full silicon removal process with faster etching and no dielectric layer damage and wafer warpage management after full silicon etching are most crucial elements to realize the SLIT technology. To manage the wafer warpage after full Si removal, a couple of knobs are identified and used such as top reinforcement layer, microbump underfill properties tuning, die thickness, die-to-die space, and total thickness adjustments. It is also discussed in the article how the wafer warpage behaves and how the wafer warpage is managed. New SLIT module shows excellent warpage characteristics of only −30 μm ∼ −40 μm at room temperature (25°C) for 25 mm × 31 mm in size and +20 μm ∼ +25 μm at reflow temperature (250°C). Thermal simulation results shows that thermal resistance of new SLIT package is almost comparable to that of standard 2000T flip-chip ball grid array (FC-BGA) package using through silicon via interposer with standard heat sink configuration and air wind condition. The reliability assessment is now under the study.

THE NEW FRAMEWORK OF APPLICATIONS: THE ALADDIN SYSTEM

2003 ◽  
Vol 12 (06) ◽  
pp. 769-781 ◽  
Author(s):  
ÁKOS ZARÁNDY ◽  
CSABA REKECZKY ◽  
PÉTER FÖLDESY ◽  
ISTVÁN SZATMÁRI
Keyword(s):  
Image Processing ◽  
High Performance ◽  
Development Time ◽  
Algorithm Development ◽  
The World ◽  
Visual Computer ◽  
New Framework

The first CNN technology-based, high performance industrial visual computer called Aladdin is reported. The revolutionary device is the world premier of the ACE4k Cellular Visual Microprocessor (CVM) chip powering an industrial visual computer. One of the most important features of the Aladdin system is the image processing library. The library reduces algorithm development time, provides efficient codes, error free operation in binary, and accurate operation in grayscale nodes. Moreover the library provides an easy way to use the Aladdin system for those who are not familiar with the CNN technology.

scholarly journals Metric Embedding Learning on Multi-Directional Projections

Algorithms ◽  
2020 ◽  
Vol 13 (6) ◽  
pp. 133 ◽  
Author(s):  
Gábor Kertész
Keyword(s):  
Feature Extraction ◽  
High Performance ◽  
Classification Performance ◽  
Difficult Problem ◽  
Input Image ◽  
Image Size ◽  
Matching Problems ◽  
Low Efficiency ◽  
Multi Class Classification ◽  
Directional Image

Image based instance recognition is a difficult problem, in some cases even for the human eye. While latest developments in computer vision—mostly driven by deep learning—have shown that high performance models for classification or categorization can be engineered, the problem of discriminating similar objects with a low number of samples remain challenging. Advances from multi-class classification are applied for object matching problems, as the feature extraction techniques are the same; nature-inspired multi-layered convolutional nets learn the representations, and the output of such a model maps them to a multidimensional encoding space. A metric based loss brings same instance embeddings close to each other. While these solutions achieve high classification performance, low efficiency is caused by memory cost of high parameter number, which is in a relationship with input image size. Upon shrinking the input, the model requires less trainable parameters, while performance decreases. This drawback is tackled by using compressed feature extraction, e.g., projections. In this paper, a multi-directional image projection transformation with fixed vector lengths (MDIPFL) is applied for one-shot recognition tasks, trained on Siamese and Triplet architectures. Results show, that MDIPFL based approach achieves decent performance, despite of the significantly lower number of parameters.

Design of a Model-Based Robot Vision VLSI Processor

1994 ◽  
Vol 6 (2) ◽  
pp. 131-136
Author(s):  
Yoshifumi Sasaki ◽  
◽  
Michitaka Kameyama
Keyword(s):  
Object Recognition ◽  
High Performance ◽  
Vision System ◽  
Robot Vision ◽  
Parallel Architecture ◽  
Computation Time ◽  
Input Image ◽  
Position Estimation ◽  
Computational Time ◽  
Model Matching

For intelligent robots, a robot vision system is usually required to perform three-dimensional (3-D) position estimation as well as object recognition at high speeds. In this paper, we propose an algorithm for 3-D object recognition and position estimation for the implementation of a VLSI processor The principle of the algorithm is based on model matching between an input image and models stored in memory. Because of enormous computation time, the development of a high-performance VLSI processor is essential. Highly parallel architecture is introduced in the VLSI processor to reduce the latency. As a result of highly parallel computing, the computational time is 10000 times faster than that of a 28.5 MIPS workstation.

scholarly journals Development of a High-Performance Adhesive with a Microphase, Separation Crosslinking Structure Using Wheat Flour and a Hydroxymethyl Melamine Prepolymer

Polymers ◽  
2019 ◽  
Vol 11 (5) ◽  
pp. 893 ◽  
Author(s):  
Jieyu Zhang ◽  
Yi Zhang ◽  
Jianzhang Li ◽  
Qiang Gao
Keyword(s):  
Shear Strength ◽  
Fracture Surface ◽  
Bond Strength ◽  
Wheat Flour ◽  
High Performance ◽  
Water Resistance ◽  
Microphase Separation ◽  
Low Cost ◽  
Bond Performance ◽  
Effective Manner

The objective of this study is to use wheat flour (WF) and hydroxymethyl melamine prepolymer (HMP) to develop a low cost, highly water-resistant, starch-based bio-adhesive for plywood fabrication. Three-layer plywood was fabricated using the resultant adhesive, and the wet shear strength of the plywood samples was measured under various conditions. After determining that water resistance was significantly improved with the addition of HMP, we evaluated the physical characteristics of the starch-based adhesive and functional groups and analyzed the thermal stability and fracture surface of the cured adhesive samples. Results showed that by adding 20 wt.% HMP into WF adhesive, the sedimentation volume in the resultant adhesive decreased by 11.3%, indicating that the increase of crosslinking in the structure of the adhesives increased the bond strength, and the wet shear strength of the resultant plywood in 63 °C water improved by 375% when compared with the WF adhesive. After increasing the addition of HMP to 40 wt.%, the wet shear strength of the resultant plywood in 100 °C water changed from 0 MPa to 0.71 MPa, which meets the exterior use plywood requirement. This water resistance and bond strength improvement resulted from (1) HMP reacting with functions in WF and forming a crosslinking structure to prevent moisture intrusion; and (2) HMP self-crosslinking and combining with crosslinked WF to form a microphase separation crosslinking structure, which improved both the crosslinking density and the toughness of the adhesive, and subsequently, the adhesive’s bond performance. In addition, the microphase separation crosslinking structure had better thermostability and created a compact ductile fracture surface, which further improved the bond performance of the adhesive. Thus, using a prepolymer to form a microphase separation crosslinking structure within the adhesive improves the rigidity, toughness, and water resistance of the material in a practical and cost-effective manner.

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