Cantilever-Type Microelectromechanical Systems Probe Card with Through-Wafer Interconnects for Fine Pitch and High-Speed Testing

2004 ◽  
Vol 43 (6B) ◽  
pp. 3877-3881 ◽  
Author(s):  
Bong-Hwan Kim ◽  
Hyun-Chul Kim ◽  
Kukjin Chun ◽  
Junghee Ki ◽  
Yongsug Tak
2012 ◽  
Vol 51 (6S) ◽  
pp. 06FL16 ◽  
Author(s):  
Bonghwan Kim ◽  
Chanseob Cho ◽  
Byeungleul Lee ◽  
Hyeon Cheol Kim ◽  
Kukjin Chun

2012 ◽  
Vol 51 ◽  
pp. 06FL16
Author(s):  
Bonghwan Kim ◽  
Chanseob Cho ◽  
Byeungleul Lee ◽  
Hyeon Cheol Kim ◽  
Kukjin Chun

Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 295
Author(s):  
Pao-Hsiung Wang ◽  
Yu-Wei Huang ◽  
Kuo-Ning Chiang

The development of fan-out packaging technology for fine-pitch and high-pin-count applications is a hot topic in semiconductor research. To reduce the package footprint and improve system performance, many applications have adopted packaging-on-packaging (PoP) architecture. Given its inherent characteristics, glass is a good material for high-speed transmission applications. Therefore, this study proposes a fan-out wafer-level packaging (FO-WLP) with glass substrate-type PoP. The reliability life of the proposed FO-WLP was evaluated under thermal cycling conditions through finite element simulations and empirical calculations. Considering the simulation processing time and consistency with the experimentally obtained mean time to failure (MTTF) of the packaging, both two- and three-dimensional finite element models were developed with appropriate mechanical theories, and were verified to have similar MTTFs. Next, the FO-WLP structure was optimized by simulating various design parameters. The coefficient of thermal expansion of the glass substrate exerted the strongest effect on the reliability life under thermal cycling loading. In addition, the upper and lower pad thicknesses and the buffer layer thickness significantly affected the reliability life of both the FO-WLP and the FO-WLP-type PoP.


2016 ◽  
Vol 2016 (DPC) ◽  
pp. 001663-001681
Author(s):  
Miguel Jimarez

We introduce a high-speed 4x25Gbps, MSA-compliant, QSFP transceiver built on a Silicon Photonics platform. The transceiver integrates high sensitivity receivers, CTLE, clock recovery, modulator drivers and BIST on a TSMC 28nm die connected to the photonic die thru a fine pitch (50um) Copper Pillar interface. A wafer-scale approach, Chip on Wafer, CoW, is used to assemble the electronic die and the light source on to the photonic die, so that the full optical path can be tested, at speed, in loopback configuration in wafer form, using a standard ATE solution. This presentation focuses on the CoW assembly development aspects of the transceiver. Wafer probe and bump, die processing services, CoW assembly and Back End of Line, BEOL, Test Services will be presented.


2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001643-001669
Author(s):  
Koji Tatsumi ◽  
Kyouhei Mineo ◽  
Takeshi Hatta ◽  
Takuma Katase ◽  
Masayuki Ishikawa ◽  
...  

Solder bumping is one of the key technologies for flip chip connection. Flip chip connection has been moving forward to its further downsizing and higher integration with new technologies, such as Cu pillar, micro bump and Through Silicon Via (TSV). Unlike some methods like solder printing and ball mounting, electroplating is a very promising technology for upcoming finer bump formation. We have been developing SnAg plating chemical while taking technology progress and customers' needs into consideration at the same time. Today, we see more variety of requests including for high speed plating to increase the productivity and also for high density packaging such as narrowing the bump pitch itself and downsizing of the bump diameter. To meet these technical needs, some adjustments of plating chemical will be necessary. This time we developed new plating chemicals to correspond to bump miniaturization. For instance, our new SnAg chemical can control bump morphology while maintaining the high deposition speed. With our new plating chemicals, we can deposit mushroom bumps that grow vertically against the resist surface, also this new chemicals work effectively to prevent short-circuit between mushroom bumps with fine pitch from forming. In addition, we succeeded in developing high speed Cu pillar plating chemicals that can control the surface morphology to create different shapes. We'd like to present our updates on controlling bump morphology for various applications.


2015 ◽  
Vol 2015 (1) ◽  
pp. 000379-000385 ◽  
Author(s):  
Brett Sawyer ◽  
Yuya Suzuki ◽  
Zihan Wu ◽  
Hao Lu ◽  
Venky Sundaram ◽  
...  

This paper describes the design, fabrication, and characterization of a two-metal layer RDL structure at 40 um pitch on thin glass interposers. Such an RDL structure is targeted at 2.5D glass interposer packages to achieve up to 1 TB/s die-to-die bandwidth and off-interposer data rates greater than 400 Gb/s, driven by consumer demand of online services for mobile devices. Advanced packaging architectures including 2.5D and 3D interposers require fine line lithography beyond the capabilities of current organic package substrates. Although silicon interposers fabricated using back-end-of-line processes can achieve these RDL wiring densities, they suffer from high electrical loss and high cost. Organic interposers with high wiring densities have also been demonstrated recently using a single sided thin film process. This paper goes beyond silicon and organic interposers in demonstrating fine pitch RDL on glass interposers fabricated by low cost, double sided, and panel-scalable processes. The high modulus and smooth surface of glass helps to achieve lithographic pitch close to that of silicon. Furthermore, the low loss tangent of glass helps in reducing dielectric losses, thus improving high-speed signal propagation. A semi-additive process flow and projection excimer laser ablation was used to fabricate two-metal layer RDL structures and bare glass RDL layers. A minimum of 3 um lithography and 20 um mico-via pitch was achieved. High-frequency characterization of these RDL structures demonstrated single-ended insertion losses of −0.097 dB/mm at f = 1 GHz and differential insertion losses of −0.05 dB/mm at f = 14 GHz.


2013 ◽  
Vol 2013 (1) ◽  
pp. 000001-000006
Author(s):  
F. Roozeboom ◽  
M. Smets ◽  
B. Kniknie ◽  
M. Hoppenbrouwers ◽  
G. Dingemans ◽  
...  

The current industrial process of choice for Deep Reactive Ion Etching (DRIE) of 3D features, e.g. Through-Silicon Vias (TSVs), Microelectromechanical Systems (MEMS), etc., is the Bosch process, which uses alternative SF6 etch cycles and C4F8-based sidewall passivation cycles in a time-sequenced mode. An alternative, potentially faster and more accurate process is to have wafers pass under spatially-divided reaction zones, which are individually separated by so-called N2-gas bearings ‘curtains’ of heights down to 10–20 μm. In addition, the feature sidewalls can be protected by replacing the C4F8-based sidewall passivation cycles by cycles forming chemisorbed and highly uniform passivation layers of Al2O3 or SiO2 deposited by Atomic Layer Deposition (ALD), also in a spatially-divided mode. ALD is performed either in thermal mode, or plasma-assisted mode in order to achieve near room-temperature processing. For metal filling of 3D-etched TSVs, or for deposition of 2D metal conductor lines one can use Laser-Induced Forward Transfer (LIFT) of metals. LIFT is a maskless, ‘solvent’-free deposition method, utilizing different types of pulsed lasers to deposit thin material (e.g. Cu, Au, Al, Cr) layers with μm-range resolution from a transparent carrier (ribbon) onto a close-by acceptor substrate. It is a dry, single-step, room temperature process in air, suitable for different types of interconnect fabrication, e.g. TSV filling and redistribution layers (RDL), without the use of wet chemistry.


2015 ◽  
Vol 661 ◽  
pp. 121-127 ◽  
Author(s):  
Yeong Lin Lai ◽  
Wen Jung Chiang

The system in a package (SiP) including of a system on a chip (SoC) and a double-data-rate-three synchronous dynamic random access memory (DDR3 SDRAM) were studied with respect to the high-speed characteristics. The SiP was the multi-chip-module thin-profile fine-pitch ball grid array (MCM TFBGA) package with four-layer substrate. The high-speed 1600-Mbps data rate DDR3 signals were used in the signal integrity (SI) analysis. The SiP with low-cost silver (Ag) wires displayed a 500.18-ps aperture width in the eye diagram, which was successfully achieved signal integrity (SI) performance requirement. This work demonstrated the SiP with the Ag wires was the great potential solution for the advanced high-speed product applications.


Sign in / Sign up

Export Citation Format

Share Document