Design and Demonstration of 40 micron Bump Pitch Multi-layer RDL on Panel-based Glass Interposers

2015 ◽  
Vol 2015 (1) ◽  
pp. 000379-000385 ◽  
Author(s):  
Brett Sawyer ◽  
Yuya Suzuki ◽  
Zihan Wu ◽  
Hao Lu ◽  
Venky Sundaram ◽  
...  
Keyword(s):  
High Speed ◽  
Metal Layer ◽  
Low Cost ◽  
Signal Propagation ◽  
Additive Process ◽  
Thin Glass ◽  
Fine Pitch ◽  
Data Rates ◽  
Insertion Losses

This paper describes the design, fabrication, and characterization of a two-metal layer RDL structure at 40 um pitch on thin glass interposers. Such an RDL structure is targeted at 2.5D glass interposer packages to achieve up to 1 TB/s die-to-die bandwidth and off-interposer data rates greater than 400 Gb/s, driven by consumer demand of online services for mobile devices. Advanced packaging architectures including 2.5D and 3D interposers require fine line lithography beyond the capabilities of current organic package substrates. Although silicon interposers fabricated using back-end-of-line processes can achieve these RDL wiring densities, they suffer from high electrical loss and high cost. Organic interposers with high wiring densities have also been demonstrated recently using a single sided thin film process. This paper goes beyond silicon and organic interposers in demonstrating fine pitch RDL on glass interposers fabricated by low cost, double sided, and panel-scalable processes. The high modulus and smooth surface of glass helps to achieve lithographic pitch close to that of silicon. Furthermore, the low loss tangent of glass helps in reducing dielectric losses, thus improving high-speed signal propagation. A semi-additive process flow and projection excimer laser ablation was used to fabricate two-metal layer RDL structures and bare glass RDL layers. A minimum of 3 um lithography and 20 um mico-via pitch was achieved. High-frequency characterization of these RDL structures demonstrated single-ended insertion losses of −0.097 dB/mm at f = 1 GHz and differential insertion losses of −0.05 dB/mm at f = 14 GHz.

Design and Demonstration of Fine-Pitch and High-Speed Redistribution Layers for Panel-Based Glass Interposers at 40-μm Bump Pitch

2016 ◽  
Vol 13 (3) ◽  
pp. 128-135
Author(s):  
Brett Sawyer ◽  
Yuya Suzuki ◽  
Zihan Wu ◽  
Hao Lu ◽  
Venky Sundaram ◽  
...  
Keyword(s):  
High Speed ◽  
Metal Layer ◽  
Low Cost ◽  
Signal Propagation ◽  
Thin Glass ◽  
Fine Pitch ◽  
Data Rates ◽  
Insertion Losses ◽  
Low Permittivity

This article analyzes redistribution layer (RDL) technologies needed for 2.5-dimensional (2.5-D) die integration on thin glass interposers and developed using low-cost processes. The design, fabrication, and characterization of a four-metal layer RDL buildup required for wide input/output (I/O) routing at 40-μm bump pitch and a two-metal layer RDL buildup fabricated directly on glass for high-speed, off-package signaling are described. Such RDL technologies are targeted at 2.5-D glass interposer packages to achieve up to 1 Tb/s die-to-die bandwidth and off-interposer data rates > 400 Gb/s, driven by consumer demand of online services for mobile devices. Advanced packaging architectures including 2.5-D and 3-D interposers require fine-line lithography beyond the capabilities of current organic package substrates. High electrical loss and high cost are characteristic of silicon interposers fabricated using back-end-of-line (BEOL) processes that can achieve RDL wiring densities required for 2.5-D die integration. Organic interposers with high wiring densities have also been demonstrated using a single-sided, thin-film process. This article goes beyond silicon and organic interposers in demonstrating fine-pitch RDL on glass interposers fabricated by low-cost, double-side, and panel-scalable processes. The high modulus and smooth surface of glass help to achieve lithographic pitch close to that of silicon. Furthermore, the low permittivity and low loss tangent of glass reduce dielectric losses, thus improving high-speed signal propagation. A semiadditive process flow and projection excimer laser ablation were used to fabricate four-metal layer (2 + 0 + 2) fine-pitch RDL and two-metal layer RDL directly on glass. A minimum of 3 μm lithography and 20 μm microvia pitch was achieved. High-frequency characterization of these RDL structures demonstrated single-ended insertion losses of −0.097 dB/mm at f = 1 GHz and differential insertion losses of −0.05 dB/mm at f = 14 GHz.

scholarly journals The Fabrication and Characterization of InAlAs/InGaAs APDs Based on a Mesa-Structure with Polyimide Passivation

Sensors ◽  
2019 ◽  
Vol 19 (15) ◽  
pp. 3399 ◽  
Author(s):  
Jheng-Jie Liu ◽  
Wen-Jeng Ho ◽  
June-Yan Chen ◽  
Jian-Nan Lin ◽  
Chi-Jen Teng ◽  
...  
Keyword(s):  
Electric Fields ◽  
High Speed ◽  
Gain Bandwidth ◽  
Mesa Structure ◽  
Multiplication Gain ◽  
Data Rates ◽  
Field Control ◽  
Side Walls ◽  
Speed Response

This paper presents a novel front-illuminated InAlAs/InGaAs separate absorption, grading, field-control and multiplication (SAGFM) avalanche photodiodes (APDs) with a mesa-structure for high speed response. The electric fields in the InAlAs-multiplication layer and InGaAs-absorption layer enable high multiplication gain and high-speed response thanks to the thickness and concentration of the field-control and multiplication layers. A mesa active region of 45 micrometers was defined using a bromine-based isotropic wet etching solution. The side walls of the mesa were subjected to sulfur treatment before being coated with a thick polyimide layer to reduce current leakage, while lowering capacitance and increasing response speeds. The breakdown voltage (VBR) of the proposed SAGFM APDs was approximately 32 V. Under reverse bias of 0.9 VBR at room temperature, the proposed device achieved dark current of 31.4 nA, capacitance of 0.19 pF and multiplication gain of 9.8. The 3-dB frequency response was 8.97 GHz and the gain-bandwidth product was 88 GHz. A rise time of 42.0 ps was derived from eye-diagrams at 0.9 VBR. There was notable absence of intersymbol-interference and the signals remained error-free at data-rates of up to 12.5 Gbps.

scholarly journals Fabrication and Characterization of Planar-Type Top-Illuminated InP-Based Avalanche Photodetector on Conductive Substrate with Operating Speeds Exceeding 10 Gbps

Sensors ◽  
2018 ◽  
Vol 18 (9) ◽  
pp. 2800 ◽  
Author(s):  
Jheng-Jie Liu ◽  
Wen-Jeng Ho ◽  
Cho-Chun Chiang ◽  
Chi-Jen Teng ◽  
Chia-Chun Yu ◽  
...  
Keyword(s):  
High Speed ◽  
Room Temperature ◽  
Modulation Frequency ◽  
Dynamic Performance ◽  
Epitaxial Structure ◽  
Data Rates ◽  
Conductive Substrate ◽  
Fabrication And Characterization ◽  
Electric Field Profile

This paper presents a high-speed top-illuminated InP-based avalanche photodetector (APD) fabricated on conductive InP-wafer using planar processes. The proposed device was then evaluated in terms of DC and dynamic performance characteristics. The design is based on a separate absorption, grading, charge, and multiplication (SAGCM) epitaxial-structure. An electric field-profile of the SAGCM layers was derived from the epitaxial structure. The punch-through voltage of the SAGCM APD was controlled to within 16–17 V, whereas the breakdown voltage (VBR) was controlled to within 28–29 V. We obtained dark current of 2.99 nA, capacitance of 0.226 pF, and multiplication gain of 12, when the APD was biased at 0.9 VBR at room temperature. The frequency-response was characterized by comparing the calculated 3-dB cut-off modulation-frequency (f3-dB) and f3-dB values measured under various multiplication gains and modulated incident powers. The time-response of the APD was evaluated by deriving eye-diagrams at 0.9 VBR using pseudorandom non-return to zero codes with a length of 231-1 at 10–12.5 Gbps. There was a notable absence of intersymbol-interference, and the signals remained error-free at data-rates of up to 12.5 Gbps. The correlation between the rise-time and modulated-bandwidth demonstrate the suitability of the proposed SAGCM-APD chip for applications involving an optical-receiver at data-rates of >10 Gbps.

Characteristics of a System in a Package with Silver Wires

2015 ◽  
Vol 661 ◽  
pp. 121-127 ◽  
Author(s):  
Yeong Lin Lai ◽  
Wen Jung Chiang
Keyword(s):  
High Speed ◽  
Low Cost ◽  
Signal Integrity ◽  
Random Access ◽  
Data Rate ◽  
Performance Requirement ◽  
Eye Diagram ◽  
Fine Pitch ◽  
Aperture Width ◽  
System On A Chip

The system in a package (SiP) including of a system on a chip (SoC) and a double-data-rate-three synchronous dynamic random access memory (DDR3 SDRAM) were studied with respect to the high-speed characteristics. The SiP was the multi-chip-module thin-profile fine-pitch ball grid array (MCM TFBGA) package with four-layer substrate. The high-speed 1600-Mbps data rate DDR3 signals were used in the signal integrity (SI) analysis. The SiP with low-cost silver (Ag) wires displayed a 500.18-ps aperture width in the eye diagram, which was successfully achieved signal integrity (SI) performance requirement. This work demonstrated the SiP with the Ag wires was the great potential solution for the advanced high-speed product applications.

A Novel Approach to the Measurement and Characterization of Losses due to Surface Roughness in High Speed Transmission Lines

2011 ◽  
Vol 2011 (CICMT) ◽  
pp. 000241-000245
Author(s):  
Femi Akinwale ◽  
A. Ege Engin
Keyword(s):  
Surface Roughness ◽  
Transmission Lines ◽  
High Speed ◽  
Data Transfer ◽  
Signal Propagation ◽  
High Frequencies ◽  
Novel Approach ◽  
Critical Issues ◽  
5 Ghz

An accurate measurement technique is required to fully characterize the losses observed at high frequencies in transmission lines. Evaluation of losses seen at high frequencies is necessary to meet the high-speed data transfer rates that future applications will demand. Conductor properties and losses are two critical issues in signal path characterization. The nature of conductor losses is not well understood at high speeds. Classical models used for predicting the effects of surface roughness on signal propagation are known to breakdown around 5 GHz. Novel methods are sought to quantify the effects beyond 5 GHz. In this paper, a simple methodology to extract conductor loss is derived and validated based on a stripline configuration of two different widths. The proposed methodology is applicable to surface roughness loss characterization of both organic and ceramic packaging materials.

Three-Dimensional Structural Characterization of Nonwoven Fabrics

2012 ◽  
Vol 18 (6) ◽  
pp. 1368-1379 ◽  
Author(s):  
Lalith B. Suragani Venu ◽  
Eunkyoung Shim ◽  
Nagendra Anantharamaiah ◽  
Behnam Pourdeyhimi
Keyword(s):  
High Speed ◽  
Imaging Technique ◽  
Low Cost ◽  
Three Dimensional ◽  
Complex Nature ◽  
Volumetric Imaging ◽  
Analysis Techniques ◽  
Nonwoven Fabrics ◽  
Nonwoven Materials

AbstractNonwoven materials are found in a gamut of critical applications. This is partly due to the fact that these structures can be produced at high speed and engineered to deliver unique functionality at low cost. The behavior of these materials is highly dependent on alignment of fibers within the structure. The ability to characterize and also to control the structure is important, but very challenging due to the complex nature of the structures. Thus, to date, focus has been placed mainly on two-dimensional analysis techniques for describing the behavior of nonwovens. This article demonstrates the utility of three-dimensional (3D) digital volumetric imaging technique for visualizing and characterizing a complex 3D class of nonwoven structures produced by hydroentanglement.

A First Room Temperature Stable and Jetable Solder Joint Encapsulant Adhesive

2011 ◽  
Vol 2011 (1) ◽  
pp. 000509-000515 ◽  
Author(s):  
Mary Liu ◽  
Wusheng Yin
Keyword(s):  
Solder Joint ◽  
High Speed ◽  
Room Temperature ◽  
Low Cost ◽  
White Paper ◽  
Solder Paste ◽  
Fine Pitch ◽  
Increasing Demand ◽  
The Right ◽  
Device Miniaturization

With the increasing demand of device miniaturization, high speed, more memory, more function, low cost, and more flexibility in device design and manufacturing chain, YINCAE has published a white paper on a first individual solder joint encapsulant which can eliminate underfilling process with at least five times solder joint increase and provide more flexibility for fine pitch and high density application. In order to meet the demand of manufacturing of high speed and low cost, YINCAE has invented a room temperature stable and jettable solder joint encapsulant adhesive – SMT 266. The invention of SMT 266 has allowed our customers to have more flexibility in their high-speed production line such as worry free on the work life of adhesive and workable jetting process. After being used in the customer field for a few years, the implementation of SMT266 has been approved improving the process yield, eliminating voids and cracks in solder joint, eliminating head-in-pillow issue for large component during lead free reflow process. The results from thermal cycling test indicated that the first failure cycles using SMT266 is high up to 6000 cycles, at least 4000 – 5000 cycles higher than other processes. The pull strength is 1.5 times higher than using solder paste plus underfilling process. All reliability data implied encapsulating each individual solder joint is the right direction to move toward. The enforcement mechanism will be discussed in our paper.

Drop Test for Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) Surface Treatment Application That is Suitable to a Low-Cost, Fine Pitch and Easy Fabrication

2009 ◽  
Author(s):  
Junehyeon Ahn ◽  
Hongkwon Kim ◽  
Kangho Byun ◽  
Youngmin Lee ◽  
Donghoon Jang ◽  
...  
Keyword(s):  
Data Acquisition ◽  
Test Performance ◽  
High Speed ◽  
Low Cost ◽  
Electroless Nickel ◽  
Drop Test ◽  
In Situ Data ◽  
Fine Pitch ◽  
Device Reliability

For an application of fine pitch Ball Grid Array (BGA) or Land Grid Array (LGA) packages, ENEPIG is a promising surface finish technology of low cost, fine pitch and easy fabrication. In this paper, we study the drop test, one of the most important items of hand held device reliability test, of ENEPIG surface finished packages. This paper focuses on the drop test performance of a bond between the main board and three kinds of packages. Those packages are designed with a daisy chain for a detection of open/short during the drop test. The main board has a bar type outline and is suitable for an In-Situ data acquisition. Drop tester is composed of a drop test unit, a high speed resistance meter and a data acquisition system (PC). JEDEC Condition B (1,500G and 0.5milliseconds duration time and half-sine pulse) in JESD22-B111 Table 1 or in JESD22-B104-C Table 1 is applied as a test condition. After the drop test, the joint geometry and the intermetallic compound (IMC) of failure samples are analyzed through the cross section method. The result shows no breaks at the solder joint of package side. All breaks, however, are originated from the solder joints of main board side. It is a significant outcome of this work to show no performance difference between ENEPIG and Electrolytic Ni/Au.

scholarly journals Towards Energy Neutral Wireless Communications: Photovoltaic Cells to Connect Remote Areas

Energies ◽  
2019 ◽  
Vol 12 (19) ◽  
pp. 3772 ◽  
Author(s):  
Das ◽  
Poves ◽  
Fakidis ◽  
Sparks ◽  
Videv ◽  
...  
Keyword(s):  
High Speed ◽  
Low Cost ◽  
Solar Panels ◽  
Free Space Optical ◽  
Solar Photovoltaics ◽  
Orkney Islands ◽  
Link Distance ◽  
Data Rates ◽  
Residential Properties ◽  
Self Powered

In this work, we have designed, developed and deployed the world’s first optical wireless communication (OWC) system using off-the-shelf lasers and solar photovoltaics. Four bidirectional OWC prototypes have been installed on the Orkney Islands of Scotland at a 30 m link distance for the provision of high-speed internet access to two residential properties. The silicon-made solar panels can harvest power up to 5 W from sunlight and they offer data rates as high as 8 Mb/s. Using additional analogue processing, data rates higher than the existing landline broadband connection are achieved. This breakthrough opens the development path to low cost, self-powered and plug-and-play free-space optical (FSO) systems.

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