A study of workload consolidation and power consumption on a multi-core processor

SRAM cells are used in many applications such as micro and multi core processor. SRAM cell improves both read stability and write ability at low supply voltage. The objective is to reduce the power dissipation of a novel low power 12T SRAM cell. This method removes half-select issue in 6T and 9T SRAM cell. This work proposes new functional low-power designs of SRAM cells with 6T, 9T and 12 transistors which operate at only 0.4V power supply in sub-threshold operation at 45 nm technology. The leakage power consumption of the proposed SRAM cell is thereby reduced compared to that of the conventional six-transistor (6T) SRAM cell. 12T cell obtains low static power dissipation.

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Diagnostics of Power Consumption of a Mobile Device Multi-Core Processor with Detail of Each Core Utilization

2020 IEEE 15th International Conference on Advanced Trends in Radioelectronics, Telecommunications and Computer Engineering (TCSET) ◽

10.1109/tcset49122.2020.235456 ◽

2020 ◽

Cited By ~ 1

Author(s):

Kateryna Obukhova ◽

Iryna Zhuravska ◽

Volodymyr Burenko

Keyword(s):

Power Consumption ◽

Mobile Device ◽

Multi Core Processor

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V-SET CACHE: AN EFFICIENT ADAPTIVE SHARED CACHE FOR MULTI-CORE PROCESSORS

Journal of Circuits System and Computers ◽

10.1142/s0218126614500959 ◽

2014 ◽

Vol 23 (07) ◽

pp. 1450095 ◽

Cited By ~ 2

Author(s):

ALI A. EL-MOURSY ◽

FADI N. SIBAI

Keyword(s):

Power Consumption ◽

Vlsi Design ◽

Dominant Factor ◽

Access Pattern ◽

Efficient Utilization ◽

The Core ◽

Area Overhead ◽

Efficient Memory ◽

Cache Design ◽

Multi Core Processor

Development in VLSI design allows multi- to many-cores to be integrated on a single microprocessor chip. This increase in the core count per chip makes it more critical to design an efficient memory sub-system especially the shared last level cache (LLC). The efficient utilization of the LLC is a dominant factor to achieve the best microprocessor throughput. Conventional set-associative cache cannot cope with the new access pattern of the cache blocks in the multi-core processors. In this paper, the authors propose a new design for LLC in multi-core processor. The proposed v-set cache design allows an adaptive and dynamic utilization of the cache blocks. Unlike lately proposed design such as v-way caches, v-set cache design limits the serial access of cache blocks. In our paper, we thoroughly study the proposed design including area and power consumption as well as the performance and throughput. On eight-core microprocessor, the proposed v-set cache design can achieve a maximum speedup of 25% and 12% and an average speedup of 16% and 6% compared to conventional n-way and v-way cache designs, respectively. The area overhead of v-set does not exceed 7% compared to n-way cache.

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A New Simulator Based on Multi Core Processor with Improved Sense Amplifier

Journal of Circuits System and Computers ◽

10.1142/s0218126615501418 ◽

2015 ◽

Vol 24 (09) ◽

pp. 1550141 ◽

Cited By ~ 2

Author(s):

Erulappan Sakthivel ◽

Veluchamy Malathi ◽

Muruganantham Arunraja

Keyword(s):

Power Consumption ◽

Low Power ◽

High Performance ◽

Routing Algorithm ◽

Main Idea ◽

Sense Amplifier ◽

Area Reduction ◽

Sense Amplifiers ◽

On Chip ◽

Multi Core Processor

In recent days, network-on-chip (NoC) researchers focus mainly on the area reduction and low power consumption both in architectural and algorithmic approach. To achieve low power and high performance in NoC architecture, sense amplifiers (SAs) introduced which can consume less power under various traffic conditions. In order to analyze the performance of architectural NoC design before fabrication level, the new simulator is developed based on multi core processor with improved sense amplifier (MCPSA) in this work. The MCPSA simulator provides user, the flexibility of incorporating various traffic configurations and routing algorithm with user reconfigurable option. In addition, the different SA model can be put into the simulation in plug and play manner for evaluation. The NoC case studies are presented to demonstrate the NoC architecture with double tail sense amplifier (DTSA) and modified-DTSA (M-DTSA) design. The performance metric such as delay, data rate and power consumption is evaluated. The main idea of this new simulator is to interface multisim environment (MSE) into a NoC environment for validating any DTSA.

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Compositional Tuning of Negative Differential Resistance in Bulk Silver Iodide Memristor

New Journal of Chemistry ◽

10.1039/d0nj05427e ◽

2020 ◽

Author(s):

SMITA GAJANAN NAIK ◽

Mohammad Hussain Kasim Rabinal

Keyword(s):

Power Consumption ◽

Negative Differential Resistance ◽

Silver Iodide ◽

Differential Resistance ◽

Fast Response ◽

Low Power Consumption ◽

Switching Effect ◽

Memory Switching ◽

Bulk Silver ◽

Emerging Memory

Electrical memory switching effect has received a great interest to develop emerging memory technology such as memristors. The high density, fast response, multi-bit storage and low power consumption are their...

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Optimal design of a high homogeneous and small-size shim coil for atomic spin gyroscope based on 0-1 linear programming

International Journal of Applied Electromagnetics and Mechanics ◽

10.3233/jae-209319 ◽

2020 ◽

Vol 64 (1-4) ◽

pp. 165-172

Author(s):

Dongge Deng ◽

Mingzhi Zhu ◽

Qiang Shu ◽

Baoxu Wang ◽

Fei Yang

Keyword(s):

Linear Programming ◽

Power Consumption ◽

Low Power ◽

Optimization Design ◽

Structural Parameters ◽

Axial Position ◽

Low Power Consumption ◽

Optimal Method ◽

Atomic Spin ◽

Shim Coil

It is necessary to develop a high homogeneous, low power consumption, high frequency and small-size shim coil for high precision and low-cost atomic spin gyroscope (ASG). To provide the shim coil, a multi-objective optimization design method is proposed. All structural parameters including the wire diameter are optimized. In addition to the homogeneity, the size of optimized coil, especially the axial position and winding number, is restricted to develop the small-size shim coil with low power consumption. The 0-1 linear programming is adopted in the optimal model to conveniently describe winding distributions. The branch and bound algorithm is used to solve this model. Theoretical optimization results show that the homogeneity of the optimized shim coil is several orders of magnitudes better than the same-size solenoid. A simulation experiment is also conducted. Experimental results show that optimization results are verified, and power consumption of the optimized coil is about half of the solenoid when providing the same uniform magnetic field. This indicates that the proposed optimal method is feasible to develop shim coil for ASG.

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Analysis of Characteristics of Halogen and LED Automobile Lamps

Light & Engineering ◽

10.33383/2019-067 ◽

2020 ◽

pp. 57-62

Author(s):

Olga Yu. Kovalenko ◽

Yulia A. Zhuravlyova

Keyword(s):

Power Consumption ◽

Flip Chip ◽

Weather Conditions ◽

Luminous Flux ◽

Luminous Efficacy ◽

Colour Temperature ◽

Study Results ◽

Calculation Results ◽

Mandatory Rules ◽

Halogen Lamps

This work contains analysis of characteristics of automobile lamps by Philips, KOITO, ETI flip chip LEDs, Osram, General Electric (GE), Gtinthebox, OSLAMPledbulbs with H1, H4, H7, H11 caps: luminous flux, luminous efficacy, correlated colour temperature. Characteristics of the studied samples are analysed before the operation of the lamps. The analysis of the calculation results allows us to make a conclusion that the values of correlated colour temperature of halogen lamps are close to the parameters declared by manufacturers. The analysis of the study results has shown that, based on actual values of correlated colour temperature, it is not advisable to use LED lamps in unfavourable weather conditions (such as rain, fog, snow). The results of the study demonstrate that there is a slight dispersion of actual values of luminous flux of halogen lamps by different manufacturers. Maximum variation between values of luminous flux of different lamps does not exceed 14 %. The analysis of the measurement results has shown that actual values of luminous flux of all halogen lamps comply with the mandatory rules specified in the UN/ECE Regulation No. 37 and luminous flux of LED lamps exceeds maximum allowable value by more than 8 %. Luminous efficacy of LED lamps is higher than that of halogen lamps: more than 82 lm/W and lower power consumption. The results of the measurements have shown that power consumption of a LED automobile lamp is lower than that of similar halogen lamps by 3 times and their luminous efficacy is higher by 5 times.

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