Diagnostics of Power Consumption of a Mobile Device Multi-Core Processor with Detail of Each Core Utilization

2020 ◽  
Author(s):  
Kateryna Obukhova ◽  
Iryna Zhuravska ◽  
Volodymyr Burenko
Keyword(s):  
Power Consumption ◽  
Mobile Device ◽  
Multi Core Processor

scholarly journals Robust 12T Sram Cell Using 45nm Technology

2020 ◽  
pp. 170-174
Author(s):  
N. Geetha Rani ◽  
N. Jyothi ◽  
P. Leelavathi ◽  
P. Deepthi Swarupa Rani ◽  
S. Reshma
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Supply ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Leakage Power ◽  
Sram Cell ◽  
Static Power ◽  
Low Supply Voltage ◽  
Multi Core Processor

SRAM cells are used in many applications such as micro and multi core processor. SRAM cell improves both read stability and write ability at low supply voltage. The objective is to reduce the power dissipation of a novel low power 12T SRAM cell. This method removes half-select issue in 6T and 9T SRAM cell. This work proposes new functional low-power designs of SRAM cells with 6T, 9T and 12 transistors which operate at only 0.4V power supply in sub-threshold operation at 45 nm technology. The leakage power consumption of the proposed SRAM cell is thereby reduced compared to that of the conventional six-transistor (6T) SRAM cell. 12T cell obtains low static power dissipation.

A2Cloud

2014 ◽  
pp. 231-261
Author(s):  
João Nuno Silva ◽  
Luís Veiga
Keyword(s):  
Power Consumption ◽  
Mobile Devices ◽  
Mobile Device ◽  
Storage Systems ◽  
Configuration File ◽  
Distributed Application ◽  
Resource Evaluation ◽  
Evaluation Mechanism ◽  
The One

This book chapter presents the integration of widely available technologies to bridge the gap between mobile devices and their computational rich surrounding environments. Taking as common glue Cloud Storage systems, new interaction between devices becomes more natural. The processing of files can be transparently executed on nearby computers, taking advantage of better hardware and saving mobile devices power. In this chapter, the authors present a novel resource evaluation mechanism, which allows a finer evaluation and more precise comparison of remote resources, leading to fewer wasted resources and better use of those resources. The use of remote resources can be performed by means of processing offloading, executing complete application on remote devices or by relocation of mobile classes. Both methods resort to the presented resource evaluation mechanism. Monolithic applications are transformed (with information from a configuration file) into distributed application, where some components execute on remote devices: nearby computers (to take advantage of existing human-computer interaction devices) or on the cloud (to speed processing). Processing offloading is accomplished by executing on nearby computers applications compatible with the one on the mobile device. This speeds that processing task (better CPU, better interaction devices), reducing the mobile device’s power consumption.

scholarly journals Adaptive Power Saving Method for Mobile Walking Guidance Device Using Motion Context

2015 ◽  
Vol 2015 ◽  
pp. 1-10
Author(s):  
Jin-Hee Lee ◽  
Yeong-Ju Lee ◽  
Minseok Song ◽  
Byeong-Seok Shin
Keyword(s):  
Power Consumption ◽  
Mobile Device ◽  
Operating Time ◽  
Power Saving ◽  
Frame Rate ◽  
Guidance System ◽  
Accelerometer Sensor ◽  
Multiple Sensors ◽  
Adaptive Power ◽  
Impaired Person

It is important to recognize the motion of the user and the surrounding environment with multiple sensors. We developed a guidance system based on mobile device for visually impaired person that helps the user to walk safely to the destination in the previous study. However, a mobile device having multiple sensors spends more power when the sensors are activated simultaneously and continuously. We propose a method for reducing the power consumption of a mobile device by considering the motion context of the user. We analyze and classify the user’s motion accurately by means of a decision tree and HMM (Hidden Markov Model) that exploit the data from a triaxial accelerometer sensor and a tilt sensor. We can reduce battery power consumption by controlling the number of active ultrasonic sensors and the frame rate of the camera used to acquire spatial context around the user. This helps us to extend the operating time of the device and reduce the weight of the device’s built-in battery.

V-SET CACHE: AN EFFICIENT ADAPTIVE SHARED CACHE FOR MULTI-CORE PROCESSORS

2014 ◽  
Vol 23 (07) ◽  
pp. 1450095 ◽  
Author(s):  
ALI A. EL-MOURSY ◽  
FADI N. SIBAI
Keyword(s):  
Power Consumption ◽  
Vlsi Design ◽  
Dominant Factor ◽  
Access Pattern ◽  
Efficient Utilization ◽  
The Core ◽  
Area Overhead ◽  
Efficient Memory ◽  
Cache Design ◽  
Multi Core Processor

Development in VLSI design allows multi- to many-cores to be integrated on a single microprocessor chip. This increase in the core count per chip makes it more critical to design an efficient memory sub-system especially the shared last level cache (LLC). The efficient utilization of the LLC is a dominant factor to achieve the best microprocessor throughput. Conventional set-associative cache cannot cope with the new access pattern of the cache blocks in the multi-core processors. In this paper, the authors propose a new design for LLC in multi-core processor. The proposed v-set cache design allows an adaptive and dynamic utilization of the cache blocks. Unlike lately proposed design such as v-way caches, v-set cache design limits the serial access of cache blocks. In our paper, we thoroughly study the proposed design including area and power consumption as well as the performance and throughput. On eight-core microprocessor, the proposed v-set cache design can achieve a maximum speedup of 25% and 12% and an average speedup of 16% and 6% compared to conventional n-way and v-way cache designs, respectively. The area overhead of v-set does not exceed 7% compared to n-way cache.

A New Simulator Based on Multi Core Processor with Improved Sense Amplifier

2015 ◽  
Vol 24 (09) ◽  
pp. 1550141 ◽  
Author(s):  
Erulappan Sakthivel ◽  
Veluchamy Malathi ◽  
Muruganantham Arunraja
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Performance ◽  
Routing Algorithm ◽  
Main Idea ◽  
Sense Amplifier ◽  
Area Reduction ◽  
Sense Amplifiers ◽  
On Chip ◽  
Multi Core Processor

In recent days, network-on-chip (NoC) researchers focus mainly on the area reduction and low power consumption both in architectural and algorithmic approach. To achieve low power and high performance in NoC architecture, sense amplifiers (SAs) introduced which can consume less power under various traffic conditions. In order to analyze the performance of architectural NoC design before fabrication level, the new simulator is developed based on multi core processor with improved sense amplifier (MCPSA) in this work. The MCPSA simulator provides user, the flexibility of incorporating various traffic configurations and routing algorithm with user reconfigurable option. In addition, the different SA model can be put into the simulation in plug and play manner for evaluation. The NoC case studies are presented to demonstrate the NoC architecture with double tail sense amplifier (DTSA) and modified-DTSA (M-DTSA) design. The performance metric such as delay, data rate and power consumption is evaluated. The main idea of this new simulator is to interface multisim environment (MSE) into a NoC environment for validating any DTSA.

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