Data Propagation Delay Constraints in Multi-Rate Systems

Author(s):  
Tobias Klaus ◽  
Florian Franzmann ◽  
Matthias Becker ◽  
Peter Ulbrich
2009 ◽  
Vol 18 (07) ◽  
pp. 1309-1320
Author(s):  
WILLIAM R. ROBERTS ◽  
DIMITRIOS VELENIS

Violations in the timing constraints of a clocked register can cause a synchronous system to malfunction. The effects of parameter variations on the timing characteristics of registers that determine the timing constraints are investigated in this paper. The sensitivity of the setup time and data propagation delay to variations in power supply voltage, temperature, and gate oxide thickness is demonstrated for four different register designs. Furthermore, design modifications are proposed that enhance the robustness of each register to variation effects.


Sensors ◽  
2021 ◽  
Vol 21 (8) ◽  
pp. 2684
Author(s):  
Sangsoo Jeong ◽  
Youngmi Baek ◽  
Sang H. Son

Vehicle platooning reduces the safety distance between vehicles and the travel time of vehicles so that it leads to an increase in road capacity and to saving fuel consumption. In Europe, many projects for vehicle platooning are being actively developed, but mostly focus on truck platooning on the highway with a simpler topology than that of the urban road. When an existing vehicle platoon is applied to urban roads, many challenges are more complicated to address than highways. They include complex topology, various routes, traffic signals, intersections, frequent lane change, and communication interference depending on a higher vehicle density. To address these challenges, we propose a distributed urban platooning protocol (DUPP) that enables high mobility and maximizes flexibility for driving vehicles to conduct urban platooning in a decentralized manner. DUPP has simple procedures to perform platooning maneuvers and does not require explicit conforming for the completion of platooning maneuvers. Since DUPP mainly operates on a service channel, it does not cause negative side effects on the exchange of basic safety messages on a control channel. Moreover, DUPP does not generate any data propagation delay due to contention-based channel access since it guarantees sequential data transmission opportunities for urban platooning vehicles. Finally, to address a problem of the broadcast storm while vehicles notify detected road events, DUPP performs forwarder selection using an analytic hierarchy process. The performance of the proposed DUPP is compared with that of ENSEMBLE which is the latest European platooning project in terms of the travel time of vehicles, the lifetime of an urban platoon, the success ratio of a designed maneuver, the external cost and the periodicity of the urban platooning-related transmissions, the adaptability of an urban platoon, and the forwarder selection ratio for each vehicle. The results of the performance evaluation demonstrate that the proposed DUPP is well suited to dynamic urban environments by maintaining a vehicle platoon as stable as possible after DUPP flexibly and quickly forms a vehicle platoon without the support of a centralized node.


MRS Bulletin ◽  
1997 ◽  
Vol 22 (10) ◽  
pp. 49-54 ◽  
Author(s):  
E. Todd Ryan ◽  
Andrew J. McKerrow ◽  
Jihperng Leu ◽  
Paul S. Ho

Continuing improvement in device density and performance has significantly affected the dimensions and complexity of the wiring structure for on-chip interconnects. These enhancements have led to a reduction in the wiring pitch and an increase in the number of wiring levels to fulfill demands for density and performance improvements. As device dimensions shrink to less than 0.25 μm, the propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant. Accordingly the interconnect delay now constitutes a major fraction of the total delay limiting the overall chip performance. Equally important is the processing complexity due to an increase in the number of wiring levels. This inevitably drives cost up by lowering the manufacturing yield due to an increase in defects and processing complexity.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILDs) and alternative architectures have surfaced to replace the current Al(Cu)/SiO2 interconnect technology. These alternative architectures will require the introduction of low-dielectric-constant k materials as the interlayer dielectrics and/or low-resistivity conductors such as copper. The electrical and thermomechanical properties of SiO2 are ideal for ILD applications, and a change to material with different properties has important process-integration implications. To facilitate the choice of an alternative ILD, it is necessary to establish general criterion for evaluating thin-film properties of candidate low-k materials, which can be later correlated with process-integration problems.


MRS Bulletin ◽  
1997 ◽  
Vol 22 (10) ◽  
pp. 19-27 ◽  
Author(s):  
Wei William Lee ◽  
Paul S. Ho

Continuing improvement of microprocessor performance historically involves a decrease in the device size. This allows greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However higher packing density requires a much larger increase in the number of interconnects. This has led to an increase in the number of wiring levels and a reduction in the wiring pitch (sum of the metal line width and the spacing between the metal lines) to increase the wiring density. The problem with this approach is that—as device dimensions shrink to less than 0.25 μm (transistor gate length)—propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. The smaller line dimensions increase the resistivity (R) of the metal lines, and the narrower interline spacing increases the capacitance (C) between the lines. Thus although the speed of the device will increase as the feature size decreases, the interconnect delay becomes the major fraction of the total delay and limits improvement in device performance.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILD) as well as alternative architectures have been proposed to replace the current Al(Cu) and SiO2 interconnect technology.


Author(s):  
Teresa V.V ◽  
Anand. B

Objective: In this research work presents an efficient way Carry Select Adder (CSLA) performance and estimation. The CSLA is utilized in several system to mitigate the issue of carry propagation delay that is happens by severally generating various carries and to get the sum, select a carry because of the uses of various pairs of RCA to provide the sum of the partial section also carry by consisting carry input but the CSLA isn't time economical, then by the multiplexers extreme total and carry is chosen in the selected section. Methodology: The fundamental plan of this work is to attain maximum speed and minimum power consumption by using Binary to Excess-1. Convertor rather than RCA within the regular CSLA. Here RCA denotes the Ripple Carry Adder section. At the span to more cut back the facility consumption, a method of CSLA with D LATCH is implemented during this research work. The look of Updated Efficient Area -Carry Select Adder (UEA-CSLA) is evaluated and intended in XILINX ISE design suite 14. 5 tools. This VLSI arrangement is utilized in picture preparing application by concluding the cerebrum tumor discovery. Conclusion: In this study, medicinal pictures estimation, investigation districts in the multi phantom picture isn't that much proficient to defeat this disadvantage here utilized hyper spectral picture method is presented a sifting procedure in VLSI innovation restriction of cerebrum tumor is performed Updated Efficient Area - Carry Select Adder propagation result dependent on Matrix Laboratory in the adaptation of R2018b.


Network ◽  
2021 ◽  
Vol 1 (1) ◽  
pp. 28-49
Author(s):  
Ehsan Ahvar ◽  
Shohreh Ahvar ◽  
Syed Mohsan Raza ◽  
Jose Manuel Sanchez Vilchez ◽  
Gyu Myoung Lee

In recent years, the number of objects connected to the internet have significantly increased. Increasing the number of connected devices to the internet is transforming today’s Internet of Things (IoT) into massive IoT of the future. It is predicted that, in a few years, a high communication and computation capacity will be required to meet the demands of massive IoT devices and applications requiring data sharing and processing. 5G and beyond mobile networks are expected to fulfill a part of these requirements by providing a data rate of up to terabits per second. It will be a key enabler to support massive IoT and emerging mission critical applications with strict delay constraints. On the other hand, the next generation of software-defined networking (SDN) with emerging cloudrelated technologies (e.g., fog and edge computing) can play an important role in supporting and implementing the above-mentioned applications. This paper sets out the potential opportunities and important challenges that must be addressed in considering options for using SDN in hybrid cloud-fog systems to support 5G and beyond-enabled applications.


Sensors ◽  
2021 ◽  
Vol 21 (9) ◽  
pp. 3000
Author(s):  
Sadeeq Jan ◽  
Eiad Yafi ◽  
Abdul Hafeez ◽  
Hamza Waheed Khatana ◽  
Sajid Hussain ◽  
...  

A significant increase has been observed in the use of Underwater Wireless Sensor Networks (UWSNs) over the last few decades. However, there exist several associated challenges with UWSNs, mainly due to the nodes’ mobility, increased propagation delay, limited bandwidth, packet duplication, void holes, and Doppler/multi-path effects. To address these challenges, we propose a protocol named “An Efficient Routing Protocol based on Master–Slave Architecture for Underwater Wireless Sensor Network (ERPMSA-UWSN)” that significantly contributes to optimizing energy consumption and data packet’s long-term survival. We adopt an innovative approach based on the master–slave architecture, which results in limiting the forwarders of the data packet by restricting the transmission through master nodes only. In this protocol, we suppress nodes from data packet reception except the master nodes. We perform extensive simulation and demonstrate that our proposed protocol is delay-tolerant and energy-efficient. We achieve an improvement of 13% on energy tax and 4.8% on Packet Delivery Ratio (PDR), over the state-of-the-art protocol.


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