AbstractPositron Annihilation Lifetime Spectroscopy (PALS) (1, 2) is a useful tool to pre-screen metal barrier integrity for Si-based porous low-k dielectrics. Pore size of low-k, thickness of metal barrier Ta, positronium (Ps) leakage from PALS, trench sidewall morphology, electrical test from one level metal (1LM) pattern wafer and Cu diffusion analysis were all correlated. Macro-porous low-k (pore size >= 200A) and large scale meso-porous low-k (>50∼200A) encounter both Ps leakage and Cu diffusion into low-k dielectric in the 0.25μmL/0.3μmS structures when using SEMATECH in-house PVD Ta 250A as barrier layer. For small scale meso-porous (>20∼50A) and micro-porous (<=20A) low-k, no Ps leakage and no Cu diffusion into low-k were observed even with PVD Ta 50A, which is proved also owing to sidewall densification to seal all sidewall pores due to plasma etch and ash. For future technology, smaller pore size of porous Si-based low-k (=< 50A) will be preferential for dense low-k like trench sidewall to avoid metal barrier integrity due to coverage problems from sidewall pores.
SIMULATION OF THE TIME-DEPENDENT DIELECTRIC BREAKDOWN IN THE METALLIZATION SYSTEM OF INTEGRATED CIRCUITS OF THE MODERN TOPOLOGICAL LEVEL