Interface Stability of Metal Barrier and low K Dielectrics

2007 ◽  
Vol 990 ◽  
Author(s):  
Toh-Ming Lu ◽  
Y. Ou ◽  
P.-I. Wang
Keyword(s):  
Metal Ions ◽  
Refractory Metal ◽  
Dielectric Material ◽  
Dielectric Materials ◽  
Processing Temperature ◽  
Electrical Stress ◽  
Bias Temperature Stress ◽  
Electric Filed ◽  
Low K ◽  
Metal Barrier

ABSTRACTIt is known that the interface between a refractory metal barrier and a dielectric material is stable against thermal treatment at a conventional IC interconnect processing temperature. However, the interface may not be stable against thermal and electrical stress called the bias temperature stress (BTS) at moderate conditions of 150 °C and 0.5 MV/cm. Massive refractory metal ions are seen to drift into low K dielectric materials that contain a mixture of organic and inorganic elements. It is argued that the oxidation of the metal at the interface creates unstable metal ions that are ready to drift into the dielectric film under an electric filed during the BTS test. Dielectric or dielectric capping materials that do not contain oxygen can prevent metal oxidation and are desirable to create a stable metal and dielectric interface.

Methods And Needs For Low K Material Research

1995 ◽  
Vol 381 ◽  
Author(s):  
Chiu H. Ting ◽  
Thomas E. Seidel
Keyword(s):  
High Performance ◽  
Process Integration ◽  
Dielectric Material ◽  
Dielectric Materials ◽  
Material Research ◽  
Material Development ◽  
Device Reliability ◽  
New Material ◽  
Speed Up ◽  
Low K

AbstractFor several years the industry has recognized the need of developing low k dielectric material and high conductivity metal for high performance interconnect. Low k dielectric will impact both power and delay favorably, while higher conductivity metal will reduce delay time. In order to be useful, new low k dielectric materials must be carefully characterized for their electrical, chemical, thermal and mechanical properties. In addition, their impact on process integration, fabrication cost and device reliability must also be considered. Since the gestation period for introducing a new material is very long, a set of standard testing methodologies are required to speed up the development process. This review will discuss various material options and the progress of material development and characterization methodologies. Example results will be provided for assessing these parameters.

The Integration of Low-k Dielectric Material Hydrogen Silsesquioxane (HSQ) with Nitride Thin Films as Barriers

2000 ◽  
Vol 612 ◽  
Author(s):  
Yuxiao Zeng ◽  
Linghui Chen ◽  
T. L. Alford
Keyword(s):  
Thin Films ◽  
Barrier Layer ◽  
Refractory Metal ◽  
Dielectric Material ◽  
Considerable Importance ◽  
Hydrogen Silsesquioxane ◽  
Barrier Layers ◽  
Vlsi Technology ◽  
Materials Used ◽  
Low K

AbstractHSQ (hydrogen silsesquioxane) is one of the promising low-k materials used in VLSI technology as an intra-metal dielectric to reduce capacitance-related issues. Like any other dielectrics, the integration of HSQ in multilevel interconnect schemes has been of considerable importance. In this study, the compatibility of HSQ with different nitride barrier layers, such as PVD and CVD TiN, PVD TaN, and CVD W2N, has been investigated by using a variety of techniques. The refractory metal barriers, Ti and Ta, are also included for a comparison. The degradation of HSQ films indicates a strong underlying barrier layer dependence. With CVD nitrides or refractory metals as barrier, HSQ exhibits a better structural and property stability than that with PVD nitrides. The possible mechanisms have been discussed to account for these observations.

Critical and Sub-critical Debonding in Nano-clustering Porous Low-k Films

2006 ◽  
Vol 914 ◽  
Author(s):  
Ryan Scott Smith ◽  
C. J. Uchibori ◽  
P. S. Ho ◽  
T. Nakamura
Keyword(s):  
Molecular Structure ◽  
Crack Growth ◽  
Adhesion Strength ◽  
Dielectric Material ◽  
Dielectric Materials ◽  
Growth Data ◽  
Critical Crack ◽  
Ambient Temperatures ◽  
Technology Roadmap ◽  
Low K

AbstractVery few porous low-k dielectric materials meet the basic requirements for integration into the back end of the line (BEOL) metallization. According to the International Technology Roadmap for Semiconductors, 2005, candidates for the 45 nm node need a k<2.2 and a minimum adhesion strength of 5 J/m2. Recently, a low-k dielectric material was developed, called nano-clustered silica (NCS). It is a spin-on glass with k<2.3. NCS is constitutively porous, with a micro- and mesopore size of ~2.8 nm. The first reported adhesion strength of this material was 10+ J/m2. We investigated the nature of the adhesive strength of NCS by critical and sub-critical fracture and Fourier Transform IR Spectroscopy (FTIR). The four-point bend technique and a mixed-mode double cantilever beam technique were employed. The sub-critical crack growth studies were performed in humid environments and ambient temperatures. Different post-treatments were used on NCS to achieve different molecular structure, as measured with FTIR. A correlation between molecular structure and critical adhesion energy was found. Atomistic parameters were calculated from the sub-critical crack growth data. A dependency of fracture behavior on post-treatment and, therefore, structure was observed.

Interfacial Adhesion Study of Porous Low-K Dielectrics to CVD Barrier Layers

2002 ◽  
Vol 716 ◽  
Author(s):  
Jeffrey A. Lee ◽  
Jeffrey T. Wetzel ◽  
Caroline Merrill ◽  
Paul S. Ho
Keyword(s):  
Mechanical Properties ◽  
Fracture Energy ◽  
Barrier Layer ◽  
Dielectric Material ◽  
Measurement Data ◽  
Dielectric Materials ◽  
Cohesive Failure ◽  
University Of Texas ◽  
Barrier Layers ◽  
Low K

AbstractThe present paper discusses the four-point bending technique employed at The University of Texas at Austin (UT Austin) to characterize adhesion strength of ultra low-k dielectric materials to CVD barrier layers. Adhesion energy between an ultra low-k dielectric material and a barrier layer was measured as a function of porosity (2.0 < k < 2.3). It was found that the fracture energy decreases with the dielectric constant, which correlates with mechanical properties such as Young's modulus and hardness. Adhesion measurement data was also obtained for different lowk / barrier layer interfaces. The independence of interfacial fracture energy on the type of interface suggests that cohesive failure occurs in the low-k material layer and not at the interface. In addition, the very low fracture energies (G < 3 J/2) confirm the weak mechanical properties of such highly porous materials. Experimental results are illustrated with analysis of failure surfaces using Auger Electron Spectroscopy and Scanning Electron Microscopy.

scholarly journals The Ultra-Low-k Dielectric Materials for Performance Improvement in Coupled Multilayer Graphene Nanoribbon Interconnects

Electronics ◽  
2019 ◽  
Vol 8 (8) ◽  
pp. 849 ◽  
Author(s):  
Peng Xu ◽  
Zhongliang Pan ◽  
Zhenhua Tang
Keyword(s):  
Delay Time ◽  
Dielectric Material ◽  
Dielectric Materials ◽  
Dielectric Medium ◽  
Graphene Nanoribbon ◽  
Noise Voltage ◽  
Multilayer Graphene ◽  
Crosstalk Noise ◽  
Characteristic Analysis ◽  
Low K

The ultra-low-k dielectric material replacing the conventional SiO2 dielectric medium in coupled multilayer graphene nanoribbon (MLGNR) interconnects is presented. An equivalent distributed transmission line model of coupled MLGNR interconnects is established to derive the analytical expressions of crosstalk delay, transfer gain, and noise output for 7.5 nm technology node at global level, which take the in-phase and out-of-phase crosstalk into account. The results show that by replacing the SiO2 dielectric mediums with the nanoglass, the maximum reduction of delay time and peak noise voltage are 25.202 ns and 0.102 V for an interconnect length of 3000 µm, respectively. It is demonstrated that the ultra-low-k dielectric materials can significantly reduce delay time and crosstalk noise and increase transfer gain compared with the conventional SiO2 dielectric medium. Moreover, it is found that the coupled MLGNR interconnect under out-of-phase mode has a larger crosstalk delay and a lesser transfer gain than that under in-phase mode, and the peak noise voltage increases with the increase of the coupled MLGNR interconnect length. The results presented in this paper would be useful to aid in the enhancement of performance of on-chip interconnects and provide guidelines for signal characteristic analysis of MLGNR interconnects.

Formation of Ultra-Thin Pore Seal Layer on Porous Low-k Films

2015 ◽  
Vol 1791 ◽  
pp. 7-13 ◽  
Author(s):  
Shoko S. Ono ◽  
Yasuhisa Kayaba ◽  
Hirofumi Tanaka ◽  
Hiroko Wachi ◽  
Koji Inoue
Keyword(s):  
Porous Material ◽  
Pore Radius ◽  
Thick Layer ◽  
Dielectric Materials ◽  
Next Generation ◽  
Low K ◽  
Metal Barrier

ABSTRACTIn order to integrate porous dielectric materials into the next generation of Cu/low-k interconnect, the porous material has to be sealed against metal barrier precursor. We have reported pore sealants which forms ultra-thin (< 3 nm-thick) layer on top of the surface of porous low-k film while the pore sealant does not diffuse into pores. In this study, it was investigated how pore seal layer is formed on the surface of porous material and how pore mouths are sealed by pore seal layer. It was found that 1) thickness of the pore seal layer is well-controlled in the range < 5 nm, by varying spin rate and concentration of solid, 2) minimal thicknesses of the pore seal layer needed to achieve an efficient sealing for porous low-k films whose pore radius is 1.5 nm was 2.6 nm. 3) Larger pores, whose pore radius is 4.2 nm, were sealed completely with an expansion of our technology.

Nondestructive Defect Imaging through Image Intensity Analysis

2007 ◽  
Author(s):  
J. Demarest ◽  
D. Bearup ◽  
A. Dalton ◽  
L. Hahn ◽  
B. Redder ◽  
...  
Keyword(s):  
Electron Beam ◽  
Dielectric Material ◽  
Natural Extension ◽  
Dielectric Materials ◽  
Intensity Analysis ◽  
Semiconductor Technology ◽  
Pixel Location ◽  
Imaging Mode ◽  
Defect Imaging ◽  
Low K

Abstract The continually shrinking dimensions of today’s semiconductor technology occasionally allow for novel approaches in imaging defects. It has become desirable to image subsurface voids prior to cross sectioning and some efforts have been made to address this need including the construction of specialized instrumentation [1]. The thickness of the metallization levels at the 65 nm technology node and smaller now allow for the use of the electron beam in a scanning electron microscope (SEM) as a material sensor. At high accelerating voltages (between 20-30 kV) in backscatter imaging mode the numerical gray level values at each pixel location can correlate to the amount of material directly under the electron beam at that location. This is particularly evident when dealing with defined geometries and material sets offering high contrast changes between materials such as those found in semiconductor technology like copper (Cu) metal and conventional dielectric materials. As a result, subsurface voids can be mapped to a reasonable representation prior to cross sectioning and precise pinpointing of the defect location in test structures can occur. This paper discusses this methodology on 65 nm technology with Cu metal lines in a low-k dielectric material for a two level metal test structure. To some extent this work represents a natural extension of a paper presented previously by the author [2].

Novel Epoxy Siloxane Polymer as Low-K Dielectric

2004 ◽  
Vol 812 ◽  
Author(s):  
Pei-I Wang ◽  
Jasbir S. Juneja ◽  
Shyam Murarka ◽  
Toh –Ming Lu ◽  
Ram Ghoshal ◽  
...  
Keyword(s):  
Current Density ◽  
Dielectric Material ◽  
Curing Temperature ◽  
Breakdown Field ◽  
Barrier Materials ◽  
Siloxane Polymer ◽  
Stress Cycles ◽  
Bias Temperature Stress ◽  
Low K ◽  
Applied Electrical Field

AbstractThis paper introduces a low-k dielectric material, a novel epoxy siloxane polymer, made by Polyset Co. Inc, which has promising properties. The polymer was spin-deposited, and thickness and optical properties were measured using variable-angle spectroscopic ellipsometry (VASE). Fourier transform infrared (FTIR) spectra of as deposited and cured polymers showed that the polymer is fully cured at 165 °C. The low curing temperature of the polymer lowers stress in back-end-of-line (BEOL) stack and thus improves the reliability. The polymer is thermally stable up to 400 °C. The polymer has Young's modulus of ∼5 GPa and hardness of greater than 0.4 GPa. After multiple stress cycles up to 300 °C, the residual stress in the polymer at room temperature is less than 60 Mpa. The polymer has good adhesion with semiconductor and dielectrics such as Si, SiC, and SiO2, metals such as Al, Cu, Co, and W, and barrier materials such as TaN. The bulk dielectric constant of the polymer is 2.4 - 2.7. The leakage current density in the polymer at the applied electrical field of 1 MV/cm is in 10−9 A/cm2 range and the breakdown field of the polymer is ranging from 5 to 7 MV/cm. The polymer when subjected to bias-temperature stress (BTS) conditions of 150 °C and 0.5 MV/cm shows no C-V shift for up to 100 min indicating that the polymer resists Copper diffusion. The current density under stress conditions of 150 °C and 0.5 MV/cm was less than 10−9 A/cm2 for up to 7 hrs.

Effects of BEOL Stack on Thermal Mechanical Stress of Cu Lines

2006 ◽  
Vol 914 ◽  
Author(s):  
Seung-Hyun Rhee ◽  
Conal E. Murray ◽  
Paul R. Besser
Keyword(s):  
Thermal Stress ◽  
Integrated Circuits ◽  
Structural Integrity ◽  
Dielectric Material ◽  
Dielectric Materials ◽  
X Ray Diffraction ◽  
And Control ◽  
Measurement And Control ◽  
Low K

AbstractThe measurement and control of the stress state in BEOL interconnects are important to ensure structural integrity and long term reliability of integrated circuits. Thermal stress in interconnects is determined by the thermal-mechanical properties of Cu lines, substrate, and dielectric materials. The effect of BEOL stacks on thermal stress characteristics of Cu lines were investigated using X-ray diffraction stress measurements. The stress characteristics of M1 and M4 level interconnects in full low-k and low-k/oxide hybrid dielectric stacks were evaluated, and the results indicated reduced substrate confinement and an increased impact of the dielectric material on in-plane stresses in higher level interconnects. The effects of dielectric stack and material properties were examined and the implication in the stresses of multilevel interconnects are discussed.

Silsesquioxane-based Photopatternable Porous Low-k Dielectric Materials

2010 ◽  
Vol 1249 ◽  
Author(s):  
Alshakim Nelson ◽  
Jitendra S Rathore ◽  
Blake Davis ◽  
Phillip Brock ◽  
Ratnam Sooriyakumaran ◽  
...  
Keyword(s):  
Semiconductor Manufacturing ◽  
Extreme Ultraviolet ◽  
Dielectric Material ◽  
Semiconductor Industry ◽  
Dielectric Materials ◽  
Patterned Structures ◽  
Sacrificial Layers ◽  
Wafer Processing ◽  
Low K ◽  
Processing Steps

AbstractThe future resolution requirements for the semiconductor industry demand advanced lithographic techniques, such as immersion and extreme ultraviolet (EUV) technologies, which will increase the cost of microelectronics manufacturing. Currently, low-k dielectric materials, which are used as insulating layers between the copper wiring, are indirectly patterned using a set of sacrificial layers and etch processes. The sacrificial layers include a photoresist polymer that must first be imaged prior to transferring the pattern to the underlying layers, including the dielectric layer. In order to reduce the number of processing steps required for semiconductor manufacturing, we have developed a novel photo-patternable low-k dielectric material that (1) eliminates the need for sacrificial layers and (2) reduces the number of wafer processing steps. Silsesquioxane copolymers that undergo acid-catalyzed crosslinking when exposed to 193nm wavelength were synthesized. In addition to the direct photo-patternability, the patterned structures are suitable as a dielectric material with a dielectric constant as low as 2.4, and an appreciable elastic modulus (E > 4.0 GPa). These photo-patternable low-k materials represent a ‘greener' approach to semiconductor manufacturing which has the ability to reduce cost, waste materials, and energy consumption.

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