scholarly journals Memory Chips with Adjustable Configurations

VLSI Design ◽  
1999 ◽  
Vol 10 (2) ◽  
pp. 203-215
Author(s):  
Lizy Kurian John

In this paper, we present the concept of Field Programmable Memory Cell Arrays (FPMCAs) as the memory counterpart to Field Programmable Gate Arrays which have proved their utility in design and rapid prototyping. Principles of dynamic reconfigurability using programmable logic and programmable interconnect are incorporated into random access memories to achieve this flexibility. We first present the design of a variable width RAM (VaWiRAM) which is a simple example of a Field Programmable Memory Cell Array. The configuration of VaWiRAMs can be adjusted by setting a few configuration pins on the memory chip. A VaWiRAM reconfigurable between widths 1 and Wmax⁡ can be constructed with the extra cost of Wmax⁡ – 1 pass gates, (Wmax⁡/2) 2-to-1 multiplexers, and ⌈log⁡2[log⁡2(k) + 1]⌉ mode pins. A novel scheme to overlap the address pins with mode control pins and achieve the mode control with only one extra pin is also presented. The paper discusses the architecture of the proposed VaWiRAMs in detail, analyzes the design tradeoffs and introduces the concept of FPMCAs.

2008 ◽  
Vol 2008 ◽  
pp. 1-9 ◽  
Author(s):  
Y. Guillemenet ◽  
L. Torres ◽  
G. Sassatelli ◽  
N. Bruchon

This paper describes the integration of field-induced magnetic switching (FIMS) and thermally assisted switching (TAS) magnetic random access memories in FPGA design. The nonvolatility of the latter is achieved through the use of magnetic tunneling junctions (MTJs) in the MRAM cell. A thermally assisted switching scheme helps to reduce power consumption during write operation in comparison to the writing scheme in the FIMS-MTJ device. Moreover, the nonvolatility of such a design based on either an FIMS or a TAS writing scheme should reduce both power consumption and configuration time required at each power up of the circuit in comparison to classical SRAM-based FPGAs. A real-time reconfigurable (RTR) micro-FPGA using FIMS-MRAM or TAS-MRAM allows dynamic reconfiguration mechanisms, while featuring simple design architecture.


Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 547 ◽  
Author(s):  
Luis Ramon Merchan-Villalba ◽  
Jose Merced Lozano-Garcia ◽  
Diego Armando de Jesus Gutierrez-Torres ◽  
Juan Gabriel Avina-Cervantes ◽  
Alejandro Pizano-Martinez

In this paper, an efficient implementation of the four-step current commutation technique for controlling bidirectional power switches in a Matrix Converter (MC) is proposed. This strategy is based on the enhanced pulse width modulation peripheral included in the C 2000 Delfino 32-bit microcontroller of Texas Instruments. By tuning the algorithmic parameters contained in this module, the four-step commutation process is carried out on the Microcontroller Unit (MCU) without overloading the full complex processor and avoiding the use of additional special hardware such as Field-Programmable Gate Arrays (FPGA) or Complex Programmable Logic Devices (CPLD) when controlling the MC. The algorithm is implemented on the TMS320F28379D MCU and operationally validated on an MC prototype, where the functionality of the proposal is demonstrated.


VLSI Design ◽  
2002 ◽  
Vol 15 (1) ◽  
pp. 397-406 ◽  
Author(s):  
Shyue-Kung Lu ◽  
Fu-Min Yeh ◽  
Jen-Sheng Shih

In this paper, we present a novel fault detection and fault diagnosis technique for Field Programmable Gate Arrays (FPGAs). The cell is configured to implement a bijective function to simplify the testing of the whole cell array. The whole chip is partitioned into disjoint one-dimensional arrays of cells. For the lookup table (LUT), a fault may occur at the memory matrix, decoder, input or output lines. The input patterns can be easily generated with a k-bit binary counter, where k denotes the number of input lines of a configurable logic block (CLB). Theoretical proofs show that the resulting fault coverage is 100%. According to the characteristics of the bijective cell function, a novel built-in self-test structure is also proposed. Our BIST approaches have the advantages of requiring less hardware resources for test pattern generation and output response analysis. To locate a faulty CLB, two diagnosis sessions are required. However, the maximum number of configurations is k + 4 for diagnosing a faulty CLB. The diagnosis complexity of our approach is also analyzed. Our results show that the time complexity is independent of the array size of the FPGA. In other words, we can make the FPGA array C-diagnosable.


Author(s):  
Madson Cruz Machado ◽  
João Viana da Fonseca Neto ◽  
José Alano Peres Abreu

Neste trabalho faz-se uma abordagem acerca do fiiltro de Kalman no que tange a sua concep-ção, modelamento matemático, algoritmo de fiiltragem e implementação em FPGA (Field Programmable Gate Arrays). Faz-se também um breve estudo sobre o dispositivo lógico programável (PLD) do tipo FPGA, sua arquitetura e suas aplicações. Após o estudo acerca do fiiltro de Kalman e sobre FPGA pas-sa-se para a etapa de embarcar o fiiltro em hardware do tipo FPGA explorando as suas características de processamento paralelo. A etapa fiinal é a validação do fiiltro executando o algoritmo de fiiltragem em FPGA usando dados reais de lançamento de foguetes balísticos. Os dados foram fornecidos pelo Centro de Lançamento de Alcântara (CLA). A principal contribuição deste trabalho é a implementação de uma arquitetura FPGA reconfigurável, garantindo uma plataforma rápida o suficiente para radares com alta precisão e boa capacidade de rastreamento de foguetes.Palavras-chave: Filtro de Kalman. FPGA. Lançamento de foguete. Filtragem.DESIGN AND IMPLEMENTATION OF KALMAN FILTER EMBEDDED IN FPGA FOR TRACKING OF BALLISTIC ROCKETABSTRACT: This work is an approach about the Kalman filter with respect to its design, mathematical modeling, filtering algorithm and implementation in FPGA (Field Programmable Gate Arrays). Also make a brief study on the programmable logic device (PLD) type FPGA, its architecture and its applications. After the study of the Kalman filter on FPGA and passes to the step of embedded on the filter in FPGA type hardware exploring its features parallel processing. The final step is to validate the filter running filtering algorithm in FPGA using real data from launching ballistic rockets. The data were provided by the Alcan-tara Launch Center (CLA). The main contribution of this work is the implementation of a reconfigurable FPGA architecture, ensuring fast enough to radar platform with high accuracy and good tracking capability rockets.KEYWORDS: Kalman filter. FPGA. Rocket launching. Filtering.DISEÑO E IMPLEMENTACIÓN DE FILTRO KALMAN EMBARCARON EN FPGA PARA DETECCIÓN DE ROCKET BALLISTICRESUMEN: Este trabajo es un enfoque sobre el filtro de Kalman con respecto a su diseño, el modelado matemático y la implementación algoritmo de filtrado en FPGA (Field Programmable Gate Arrays). Tambi-én hace un breve estudio sobre el dispositivo lógico programable (PLD) tipo FPGA, su arquitectura y sus aplicaciones. Tras el estudio del filtro de Kalman en FPGA pasa a la etapa de embarcarse en la FPGA hardware tipo de filtro explorar sus características de procesamiento paralelo. El último paso es validar el filtro funcionando algoritmo de filtrado en FPGA utilizando datos reales de lanzamiento de cohetes balísti-cos. Los datos fueron proporcionados por el Centro de Lanzamiento de Alcántara (CLA). La principal con-tribución de este trabajo es la implementación de una arquitectura FPGA reconfigurable, asegurando la suficiente rapidez a la plataforma de radar con alta precisión y buenos cohetes capacidad de seguimiento.PALABRAS CLAVE: Filtro de Kalman. FPGA. Cohete de lanzamiento. El filtrado.


Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 584 ◽  
Author(s):  
Muhammad Irfan ◽  
Zahid Ullah ◽  
Ray C. C. Cheung

Content-addressable memory (CAM) is a type of associative memory, which returns the address of a given search input in one clock cycle. Many designs are available to emulate the CAM functionality inside the re-configurable hardware, field-programmable gate arrays (FPGAs), using static random-access memory (SRAM) and flip-flops. FPGA-based CAMs are becoming popular due to the rapid growth in software defined networks (SDNs), which uses CAM for packet classification. Emulated designs of CAM consume much dynamic power owing to a high amount of switching activity and computation involved in finding the address of the search key. In this paper, we present a power and resource efficient binary CAM architecture, Zi-CAM, which consumes less power and uses fewer resources than the available architectures of SRAM-based CAM on FPGAs. Zi-CAM consists of two main blocks. RAM block (RB) is activated when there is a sequence of repeating zeros in the input search word; otherwise, lookup tables (LUT) block (LB) is activated. Zi-CAM is implemented on Xilinx Virtex-6 FPGA for the size 64 × 36 which improved power consumption and hardware cost by 30 and 32%, respectively, compared to the available FPGA-based CAMs.


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