scholarly journals Zi-CAM: A Power and Resource Efficient Binary Content-Addressable Memory on FPGAs

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 584 ◽  
Author(s):  
Muhammad Irfan ◽  
Zahid Ullah ◽  
Ray C. C. Cheung
Keyword(s):  
Clock Cycle ◽  
Random Access ◽  
Packet Classification ◽  
Switching Activity ◽  
Content Addressable Memory ◽  
Gate Arrays ◽  
Lut Block ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Configurable Hardware

Content-addressable memory (CAM) is a type of associative memory, which returns the address of a given search input in one clock cycle. Many designs are available to emulate the CAM functionality inside the re-configurable hardware, field-programmable gate arrays (FPGAs), using static random-access memory (SRAM) and flip-flops. FPGA-based CAMs are becoming popular due to the rapid growth in software defined networks (SDNs), which uses CAM for packet classification. Emulated designs of CAM consume much dynamic power owing to a high amount of switching activity and computation involved in finding the address of the search key. In this paper, we present a power and resource efficient binary CAM architecture, Zi-CAM, which consumes less power and uses fewer resources than the available architectures of SRAM-based CAM on FPGAs. Zi-CAM consists of two main blocks. RAM block (RB) is activated when there is a sequence of repeating zeros in the input search word; otherwise, lookup tables (LUT) block (LB) is activated. Zi-CAM is implemented on Xilinx Virtex-6 FPGA for the size 64 × 36 which improved power consumption and hardware cost by 30 and 32%, respectively, compared to the available FPGA-based CAMs.

scholarly journals On the Use of Magnetic RAMs in Field-Programmable Gate Arrays

2008 ◽  
Vol 2008 ◽  
pp. 1-9 ◽  
Author(s):  
Y. Guillemenet ◽  
L. Torres ◽  
G. Sassatelli ◽  
N. Bruchon
Keyword(s):  
Power Consumption ◽  
Random Access ◽  
Switching Scheme ◽  
Fpga Design ◽  
Gate Arrays ◽  
Magnetic Switching ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Time Required ◽  
Magnetic Tunneling

This paper describes the integration of field-induced magnetic switching (FIMS) and thermally assisted switching (TAS) magnetic random access memories in FPGA design. The nonvolatility of the latter is achieved through the use of magnetic tunneling junctions (MTJs) in the MRAM cell. A thermally assisted switching scheme helps to reduce power consumption during write operation in comparison to the writing scheme in the FIMS-MTJ device. Moreover, the nonvolatility of such a design based on either an FIMS or a TAS writing scheme should reduce both power consumption and configuration time required at each power up of the circuit in comparison to classical SRAM-based FPGAs. A real-time reconfigurable (RTR) micro-FPGA using FIMS-MRAM or TAS-MRAM allows dynamic reconfiguration mechanisms, while featuring simple design architecture.

scholarly journals Area Optimisation for Field-Programmable Gate Arrays in SystemC Hardware Compilation

2008 ◽  
Vol 2008 ◽  
pp. 1-14
Author(s):  
Johan Ditmar ◽  
Steve McKeever ◽  
Alex Wilson
Keyword(s):  
Clock Cycle ◽  
Gate Arrays ◽  
Field Programmable ◽  
Separate Block ◽  
Programmable Gate Arrays ◽  
Source Level ◽  
High Level ◽  
Specific Implementation ◽  
Mapping Arrays ◽  
Language Construct

This paper discusses a pair of synthesis algorithms that optimise a SystemC design to minimise area when targeting FPGAs. Each can significantly improve the synthesis of a high-level language construct, thus allowing a designer to concentrate more on an algorithm description and less on hardware-specific implementation details. The first algorithm is a source-level transformation implementing function exlining—where a separate block of hardware implements a function and is shared between multiple calls to the function. The second is a novel algorithm for mapping arrays to memories which involves assigning array accesses to memory ports such that no port is ever accessed more than once in a clock cycle. This algorithm assigns accesses to read/write only ports and read-write ports concurrently, solving the assignment problem more efficiently for a wider range of memories compared to existing methods. Both optimisations operate on a high-level program representation and have been implemented in a commercial SystemC compiler. Experiments show that in suitable circumstances these techniques result in significant reductions in logic utilisation for FPGAs.

scholarly journals Memory Chips with Adjustable Configurations

VLSI Design ◽  
1999 ◽  
Vol 10 (2) ◽  
pp. 203-215
Author(s):  
Lizy Kurian John
Keyword(s):  
Random Access ◽  
Memory Cell ◽  
Programmable Logic ◽  
Cell Array ◽  
Gate Arrays ◽  
Mode Control ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Cell Arrays ◽  
Design Tradeoffs

In this paper, we present the concept of Field Programmable Memory Cell Arrays (FPMCAs) as the memory counterpart to Field Programmable Gate Arrays which have proved their utility in design and rapid prototyping. Principles of dynamic reconfigurability using programmable logic and programmable interconnect are incorporated into random access memories to achieve this flexibility. We first present the design of a variable width RAM (VaWiRAM) which is a simple example of a Field Programmable Memory Cell Array. The configuration of VaWiRAMs can be adjusted by setting a few configuration pins on the memory chip. A VaWiRAM reconfigurable between widths 1 and Wmax⁡ can be constructed with the extra cost of Wmax⁡ – 1 pass gates, (Wmax⁡/2) 2-to-1 multiplexers, and ⌈log⁡2[log⁡2(k) + 1]⌉ mode pins. A novel scheme to overlap the address pins with mode control pins and achieve the mode control with only one extra pin is also presented. The paper discusses the architecture of the proposed VaWiRAMs in detail, analyzes the design tradeoffs and introduces the concept of FPMCAs.

scholarly journals RESTful Web Services on Standalone Disaggregated FPGAs

2021 ◽  
Author(s):  
Raphael Polig ◽  
Jagath Weerasinghe ◽  
Christoph Hagleitner
Keyword(s):  
Web Services ◽  
Web Service ◽  
Language Processing ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Configurable Hardware ◽  
Restful Web Services ◽  
Cloud Applications ◽  
Server Infrastructure

We present an architecture for field-programmable gate arrays (FPGAs) to expose RESTful web services. This architecture allows clients to access accelerated web services from any platform and programming language that can perform RESTful API calls. By using this architecture, the client's application benefits from a high throughput and low latency web service interface. Traditionally, FPGAs are deployed in CPU-centric infrastructures as worker devices in the form of accelerators. However, for FPGA-centric applications, the overhead of a host CPU diminishes the performance, scalability and energy efficiency. cloudFPGA solves these issues by deploying FPGAs as standalone, disaggregated resources in the DC. Building on top of the cloudFPGA platform, the presented architecture simplifies the integration of FPGA-accelerated functions with cloud applications. A configurable hardware block that can be generated from an OpenAPI-based specification of the web service is used to deploy an FPGA-based application. We compare a natural language processing (NLP) application that is exposed as a web service using the traditional server infrastructure and our RESTful service layer. Measurements show an improvement of 20x in terms of throughput and 4x reduction in mean latency.

A novel addressing algorithm of radix-2 FFT using single-bank dual-port memory

Circuit World ◽  
2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Zeynep Kaya ◽  
Erol Seke
Keyword(s):  
Design Methodology ◽  
Clock Cycle ◽  
Memory Location ◽  
Content Type ◽  
Gate Arrays ◽  
Memory Block ◽  
Fft Processor ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Single Block

Purpose This paper aims to present a single-block memory-based FFT processor design with a conflict-free addressing scheme for field-programmable gate arrays FPGAs with dual-port block memories. This study aims for a single-block dual-port memory-based N-point radix-2 FFT design that uses memory locations and spending minimum clock cycle. Design/methodology/approach A new memory-based Fast Fourier Transform (FFT) design that uses a dual-port memory block is proposed. Dual-port memory allows the design to perform two memory reads and writes in a single clock cycle. This approach achieves low operational clock and smallest memory simultaneously, excluding some small overhead for exceptional address changes. The methodology is to read from while writing to a memory location, eliminating the need for excess memory and additional clock cycles. Findings With the minimum memory size and the simplest architecture, radix-2 FFT and single-memory block are used. The number of clock pulses spent for all FFT operations does not provide much advantage for low-point FFT operations but is important for high-point FFT operations. With the developed algorithm, N memory is used, and the number of clock pulses spent for all FFT stages is (N/2 +1)log2N for all FFT operations. Originality/value This is an original paper, which has simultaneously in whole or in part been submitted anywhere else.

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