scholarly journals Companding Realizations of the Nonlinear Energy Operator

2013 ◽  
Vol 2013 ◽  
pp. 1-7 ◽  
Author(s):  
Andreas-Christos Demartinos ◽  
Chrysostomos Kasimis ◽  
Costas Laoudias ◽  
Costas Psychalinos
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Energy Operator ◽  
Efficient Design ◽  
Design Environment ◽  
Power Supply Voltage ◽  
Comparison Results ◽  
Log Domain ◽  
Nonlinear Energy ◽  
Nonlinear Energy Operator

Realizations of the nonlinear energy operator (NEO), using the concept of companding filtering, are introduced and compared in this work. For this purpose, the Log-Domain and Sinh-Domain filtering techniques have been followed. Both topologies are constructed from differentiator and multiplier blocks which have been realized through the utilization of nonlinear transconductor cells. Both of the proposed topologies offer the capability of ultra-low voltage operation, thanks to the employment of MOS transistors in the weak inversion. Considering a single power supply voltage of 0.5 V, the behavior of the proposed NEO realizations has been simulated using the Analog Design Environment of the Cadence software and the design kit of the TSMC 130 nm process. Comparison results show that the Sinh-Domain realization offers a more power efficient design than that offered by the Log-Domain realization.

scholarly journals 0.5 V Cardiac Sense Amplifier Realization Using Log-Domain Filtering

2013 ◽  
Vol 2013 ◽  
pp. 1-11 ◽  
Author(s):  
Christos Giagkoulovits ◽  
Costas Psychalinos
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Cmos Process ◽  
Operating Voltage ◽  
Design Environment ◽  
Power Supply Voltage ◽  
Sense Amplifier ◽  
Dc Power ◽  
Analog Part ◽  
Log Domain

A novel configuration of a cardiac sense amplifier for pacemakers, realized using the concept of Log-Domain filtering, is introduced in this paper. The analog part of the amplifier operates under a single 0.5 V power supply voltage. Compared to the corresponding already published configuration, the proposed scheme offers the benefits of reduced operating voltage and dc power dissipation. The performance of the intermediate stages, as well as of the whole system, has been evaluated through the utilization of the Analog Design Environment of the Cadence software and, also, the design kit provided by the AMS 0.35 μm CMOS process.

scholarly journals Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs

Electronics ◽  
2021 ◽  
Vol 10 (10) ◽  
pp. 1156
Author(s):  
Lorenzo Benvenuti ◽  
Alessandro Catania ◽  
Giuseppe Manfredini ◽  
Andrea Ria ◽  
Massimo Piotto ◽  
...  
Keyword(s):  
Low Voltage ◽  
Flicker Noise ◽  
Supply Voltage ◽  
Cmos Process ◽  
Clock Frequency ◽  
Design Environment ◽  
Ultra Low Power ◽  
Analog Cmos ◽  
Gain Error ◽  
Dc Gain

The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage ΔΣ modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based ΔΣ modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the CadenceTM design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.

scholarly journals Low-voltage, low-power and high gain cmosota using active positive feedback with feed forward and FDCM techniques

2002 ◽  
Vol 15 (1) ◽  
pp. 93-101
Author(s):  
Lyes Bouzerara ◽  
Tahar Belaroussi ◽  
Boualem Amirouche
Keyword(s):  
Positive Feedback ◽  
Low Voltage ◽  
Supply Voltage ◽  
Phase Margin ◽  
Current Mirror ◽  
Power Supply Voltage ◽  
Gain Bandwidth ◽  
Frequency Dependent ◽  
Feed Forward ◽  
Current Mirrors

A low voltage, high dc gain and wideband load compensated cas code operational transconductance amplifier (OTA), using an active positive feedback with feed forward technique and frequency-dependent current mirrors (FDCM), is presented and analyzed. Such techniques stand as a powerful method of gain bandwidth and phase margin enhancements. In this paper, a frequency-dependent current mirror, whose input impedance increases with frequency, is used to form the feed forward path at the input of the current mirror with a feed forward capacitor. By using these techniques, the gain bandwidth product of the amplifier is improved from 115 MHz to 194 MHz, the phase margin is also improved from 85? to 95? and the gain is enhanced from 11 dB to 93 dB. This amplifier operates at 2.5 V power supply voltage drives a capacitive load of 1pF and gives a power dissipation of 7 mW. The predicted performance is verified by simulations using HSPICE tool with 0.8 fim CMOS AMS parameters.

scholarly journals Ultra-Low-Voltage Inverter-Based Operational Transconductance Amplifiers with Voltage Gain Enhancement by Improved Composite Transistors

Electronics ◽  
2020 ◽  
Vol 9 (9) ◽  
pp. 1410
Author(s):  
Luis Henrique Rodovalho ◽  
Orazio Aiello ◽  
Cesar Ramos Rodrigues
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Voltage Gain ◽  
Design Environment ◽  
Operational Transconductance Amplifiers ◽  
Gain Enhancement ◽  
Transconductance Amplifiers ◽  
Forward Body Bias ◽  
The Cost ◽  
The Impact

This paper proposes topological enhancements to increase voltage gain of ultra-low-voltage (ULV) inverter-based OTAs. The two proposed improvements rely on adoption of composite transistors and forward-body-biasing. The impact of the proposed techniques on performance figures is demonstrated through simulations of two OTAs. The first OTA achieves a 39 dB voltage gain, with a power consumption of 600 pW and an active area of 447 μm2. The latter allies the forward-body-bias approach with the benefit of the independently biased composite transistors. By combining both solutions, voltage gain is raised to 51 dB, consuming less power (500 pW) at the cost of an increased area of 727 μm2. The validation has been performed through post-layout simulations with the Cadence Analog Design Environment and the TSMC 180 nm design kit, with the supply voltage ranging from 0.3 V to 0.6 V.

scholarly journals Low-voltage 0.35-/mi cmos wideband operational transconductance amplifier

2002 ◽  
Vol 15 (3) ◽  
pp. 361-369
Author(s):  
Lyes Bouzerara ◽  
Mohand Belaroussi
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Output Impedance ◽  
Power Supply Voltage ◽  
Gain Bandwidth ◽  
Current Mirrors ◽  
Transconductance Amplifier ◽  
Cascade Structure ◽  
Feedback Frequency ◽  
High Output Impedance

A low voltage CMOS wideband operational Tran conductance amplifier (OTA) using regulated cascade structure with an active positive feedback frequency-dependent current mirrors and feed forward techniques, is presented and analyzed. Such techniques stand as a powerful method of gain bandwidth, output impedance and phase margin enhancements. In this paper, an efficient implementation of a high output impedance current mirror is used in the design of an OTA by means of the regulated cascade circuits. This amplifier operates at ?1.25 V power supply voltage, exhibits a voltage gain of 68 dB, and provides a gain bandwidth product of 166 MHz. It drives a capacitive load of 1.6 pF and gives a power dissipation of 8.5 mW. The predicted performance is verified by simulations using HSPICE tool with 0.35 /itm CMOS TSMC parameters.

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