scholarly journals Full-Phase Operation Transresistance-Mode Precision Full-Wave Rectifier Designs Using Single Operational Transresistance Amplifier

2019 ◽  
Vol 2019 ◽  
pp. 1-18 ◽  
Author(s):  
Hung-Chun Chien

This study proposed the designs of two full-phase operation transresistance-mode (TRM) precision full-wave rectifiers. The first circuit consisted of a single operational transresistance amplifier (OTRA), four diodes, and a resistor. The second scheme was an OTRA combined with a full metal-oxide semiconductor field-effect transistor-based design, which is preferable for integrated circuit implementation because no passive components are used in the circuit topology. Based on our literature review, this is the first study that discussed a full-phase operation transresistance-mode precision full-wave rectifier consisting of a single OTRA and few passive components. In this paper, several previously reported precision full-wave rectifiers consisting of various active devices are first reviewed followed by the proposed OTRA-based transresistance-mode precision full-wave rectifiers and an analysis of nonideal effects. Furthermore, computer simulations and experimental results are presented to verify the validity of the proposed circuits, which were consistent with the theoretical predictions.

Materials ◽  
2021 ◽  
Vol 14 (9) ◽  
pp. 2316
Author(s):  
Kalparupa Mukherjee ◽  
Carlo De Santi ◽  
Matteo Borga ◽  
Karen Geens ◽  
Shuzhen You ◽  
...  

The vertical Gallium Nitride-on-Silicon (GaN-on-Si) trench metal-oxide-semiconductor field effect transistor (MOSFET) is a promising architecture for the development of efficient GaN-based power transistors on foreign substrates for power conversion applications. This work presents an overview of recent case studies, to discuss the most relevant challenges related to the development of reliable vertical GaN-on-Si trench MOSFETs. The focus lies on strategies to identify and tackle the most relevant reliability issues. First, we describe leakage and doping considerations, which must be considered to design vertical GaN-on-Si stacks with high breakdown voltage. Next, we describe gate design techniques to improve breakdown performance, through variation of dielectric composition coupled with optimization of the trench structure. Finally, we describe how to identify and compare trapping effects with the help of pulsed techniques, combined with light-assisted de-trapping analyses, in order to assess the dynamic performance of the devices.


Materials ◽  
2021 ◽  
Vol 14 (13) ◽  
pp. 3554
Author(s):  
Jaeyeop Na ◽  
Jinhee Cheon ◽  
Kwangsoo Kim

In this paper, a novel 4H-SiC split heterojunction gate double trench metal-oxide-semiconductor field-effect transistor (SHG-DTMOS) is proposed to improve switching speed and loss. The device modifies the split gate double trench MOSFET (SG-DTMOS) by changing the N+ polysilicon split gate to the P+ polysilicon split gate. It has two separate P+ shielding regions under the gate to use the P+ split polysilicon gate as a heterojunction body diode and prevent reverse leakage `current. The static and most dynamic characteristics of the SHG-DTMOS are almost like those of the SG-DTMOS. However, the reverse recovery charge is improved by 65.83% and 73.45%, and the switching loss is improved by 54.84% and 44.98%, respectively, compared with the conventional double trench MOSFET (Con-DTMOS) and SG-DTMOS owing to the heterojunction.


1987 ◽  
Vol 65 (8) ◽  
pp. 995-998
Author(s):  
N. G. Tarr

It is shown that the accuracy of the charge-sheet model for the long-channel metal-oxide-semiconductor field-effect transistor can be improved by allowing for the small potential drop across the inversion layer, and by using a more accurate analytic approximation for the charge stored in the depletion region.


2008 ◽  
Vol 1144 ◽  
Author(s):  
Pranav Garg ◽  
Yi Hong ◽  
Md. Mash-Hud Iqbal ◽  
Stephen J. Fonash

ABSTRACTRecently, we have experimentally demonstrated a very simply structured unipolar accumulation-type metal oxide semiconductor field effect transistor (AMOSFET) using grow-in-place silicon nanowires. The AMOSFET consists of a single doping type nanowire, metal source and drain contacts which are separated by a partially gated region. Despite its simple configuration, it is capable of high performance thereby offering the potential of a low manufacturing-cost transistor. Since the quality of the metal/semiconductor ohmic source and drain contacts impacts AMOSFET performance, we repot here on initial exploration of contact variations and of the impact of thermal process history. With process optimization, current on/off ratios of 106 and subthreshold swings of 70 mV/dec have been achieved with these simple devices


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