scholarly journals A review paper on memory fault models and test algorithms

2021 ◽  
Vol 10 (6) ◽  
pp. 3083-3093
Author(s):  
Aiman Zakwan Jidin ◽  
Razaidi Hussin ◽  
Lee Weng Fook ◽  
Mohd Syafiq Mispan
Keyword(s):  
Review Paper ◽  
Deep Submicron ◽  
Memory Testing ◽  
Fault Models ◽  
March Test ◽  
Detection Ability ◽  
Test Operation ◽  
Testing Algorithms ◽  
Self Test ◽  
Embedded Memories

Testing embedded memories in a chip can be very challenging due to their high-density nature and manufactured using very deep submicron (VDSM) technologies. In this review paper, functional fault models which may exist in the memory are described, in terms of their definition and detection requirement. Several memory testing algorithms that are used in memory built-in self-test (BIST) are discussed, in terms of test operation sequences, fault detection ability, and also test complexity. From the studies, it shows that tests with 22 N of complexity such as March SS and March AB are needed to detect all static unlinked or simple faults within the memory cells. The N in the algorithm complexity refers to Nx*Ny*Nz whereby Nx represents the number of rows, Ny represents the number of columns and Nz represents the number of banks. This paper also looks into optimization and further improvement that can be achieved on existing March test algorithms to increase the fault coverage or to reduce the test complexity.

scholarly journals BIST Analysis of an Embedded Memory Associated Logic

VLSI Design ◽  
2001 ◽  
Vol 12 (4) ◽  
pp. 563-578
Author(s):  
Jacob Savir
Keyword(s):  
Design Rule ◽  
Random Pattern ◽  
Data Path ◽  
Embedded Memory ◽  
Control Logic ◽  
Simulation Tools ◽  
Cutting Algorithm ◽  
Self Test ◽  
And Control ◽  
Embedded Memories

Of late some interesting and useful work has been done on the problem of testing logic surrounding embedded memories. This work assumes that the logic surrounding the memory is functionally partitioned and that the different partitions are logically isolated one from the other.This paper expands upon past work using a more flexible design rule which allows feed-forward connections between the data-path Prelogic and Postlogic. The connections are such that there is no feedback from the memory outputs to its inputs, and both the Prelogic and the Postlogic are disconnected from the Address and Control logic. Under this design rule we show the auxiliary circuits used to determine the random pattern testability of faults in the circuitry driving the address inputs and the controls of the two-port memory.The techniques described herein are intended to be used in conjunction with the cutting algorithm for testability measurement in built-in self-test (BIST) designs [2, 11, 17], but may also be suitable for use with other detection probability tools [9, 19], and simulation tools [20].

scholarly journals Analysis of multibackground memory testing techniques

2010 ◽  
Vol 20 (1) ◽  
pp. 191-205 ◽  
Author(s):  
Ireneusz Mrozek
Keyword(s):  
Initial Conditions ◽  
Fault Coverage ◽  
Fault Model ◽  
Memory Testing ◽  
March Test ◽  
Transition Faults ◽  
Complex Fault ◽  
Pattern Sensitive Faults ◽  
Testing Techniques ◽  
March Tests

Analysis of multibackground memory testing techniquesMarch tests are widely used in the process of RAM testing. This family of tests is very efficient in the case of simple faults such as stuck-at or transition faults. In the case of a complex fault model—such as pattern sensitive faults—their efficiency is not sufficient. Therefore we have to use other techniques to increase fault coverage for complex faults. Multibackground memory testing is one of such techniques. In this case a selected March test is run many times. Each time it is run with new initial conditions. One of the conditions which we can change is the initial memory background. In this paper we compare the efficiency of multibackground tests based on four different algorithms of background generation.

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