scholarly journals Design of Low Power Low Noise Amplifier using Gm-boosted Technique

2018 ◽  
Vol 9 (3) ◽  
pp. 685 ◽  
Author(s):  
Maizan Muhamad ◽  
Norhayati Soin ◽  
Harikrishnan Ramiah
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
Integrated Circuit ◽  
Wireless Lan ◽  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Center Frequency ◽  
Design Specifications ◽  
Noise Amplifier

This paper presents the development of low noise amplifier integrated circuit using 130nm RFCMOS technology. The low noise amplifier function is to amplify extremely low noise amplifier without adding noise and preserving required signal to a noise ratio. A detailed methodology and analysis that leads to a low power LNA are being discussed throughout this paper. Inductively degenerated and Gm-boosted topology are used to design the circuit. Design specifications are focused for 802.11b/g/n IEEE Wireless LAN Standards with center frequency of 2.4 GHz. The best low noise amplifier provides a power gain (S21) of 19.841 dB with noise figure (NF) of 1.497 dB using the gm-boosted topology while the best low power amplifier drawing 4.19mW power from a 1.2V voltage supply using the inductively degenerated.

Optimized Design of Low Power Complementary Metal Oxide Semiconductor Low Noise Amplifier for Zigbee Application

2021 ◽  
Vol 18 (4) ◽  
pp. 1327-1330
Author(s):  
S. Manjula ◽  
R. Karthikeyan ◽  
S. Karthick ◽  
N. Logesh ◽  
M. Logeshkumar
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Supply Voltage ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Oxide Semiconductor ◽  
Design System ◽  
Cmos Process ◽  
Design Specifications ◽  
Noise Amplifier

An optimized high gain low power low noise amplifier (LNA) is presented using 90 nm CMOS process at 2.4 GHz frequency for Zigbee applications. For achieving desired design specifications, the LNA is optimized by particle swarm optimization (PSO). The PSO is successfully implemented for optimizing noise figure (NF) when satisfying all the design specifications such as gain, power dissipation, linearity and stability. PSO algorithm is developed in MATLAB to optimize the LNA parameters. The LNA with optimized parameters is simulated using Advanced Design System (ADS) Simulator. The LNA with optimized parameters produces 21.470 dB of voltage gain, 1.031 dB of noise figure at 1.02 mW power consumption with 1.2 V supply voltage. The comparison of designed LNA with and without PSO proves that the optimization improves the LNA results while satisfying all the design constraints.

scholarly journals Linearity improvement of differential CMOS low noise amplifier

2019 ◽  
Vol 14 (1) ◽  
pp. 407
Author(s):  
Maizan Muhamad ◽  
Norhayati Soin ◽  
Harikrishnan Ramiah
Keyword(s):  
Integrated Circuit ◽  
Wireless Lan ◽  
Noise Figure ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Common Source ◽  
Linearity Improvement ◽  
Noise Amplifier

<p>This paper presents the linearity improvement of differential CMOS low noise amplifier integrated circuit using 0.13um CMOS technology. In this study, inductively degenerated common source topology is adopted for wireless LAN application. The linearity of the single-ended LNA was improved by using differential structures with optimum biasing technique. This technique achieved better LNA and linearity performance compare with single-ended structure. Simulation was made by using the cadence spectre RF tool. Consuming 5.8mA current at 1.2V supply voltage, the designed LNA exhibits S<sub>21</sub> gain of 18.56 dB, noise figure (NF) of 1.85 dB, S<sub>11</sub> of −27.63 dB, S<sub>22</sub> of -34.33 dB, S<sub>12</sub> of −37.09 dB and IIP3 of -7.79 dBm.</p>

scholarly journals Design of Low Power UWB CMOS Low Noise Amplifier using Active Inductor for WLAN Receiver

2018 ◽  
Vol 7 (2.24) ◽  
pp. 448
Author(s):  
S Manjula ◽  
M Malleshwari ◽  
M Suganthy
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Wide Band ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Design System ◽  
Active Inductor ◽  
Chip Area ◽  
Noise Amplifier

This paper presents a low power Low Noise Amplifier (LNA) using 0.18µm CMOS technology for ultra wide band (UWB) applications. gm boosting common gate (CG) LNA is designed to improve the noise performance.  For the reduction of on chip area, active inductor is employed at the input side of the designed LNA for input impedance matching. The proposed UWB LNA is designed using Advanced Design System (ADS) at UWB frequency of 3.1-10.6 GHz. Simulation results show that the gain of 10.74+ 0.01 dB, noise figure is 4.855 dB, input return loss <-13 dB and 12.5 mW power consumption.  

scholarly journals Research and Design of X-band Low Noise Amplifier Based on CMOS Process

2021 ◽  
Vol 2108 (1) ◽  
pp. 012102
Author(s):  
Chao Ma ◽  
Hongjiang Wu ◽  
Xudong Lu ◽  
Haitao Sun
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Center Frequency ◽  
Cmos Process ◽  
Actual Measurement ◽  
Chip Area ◽  
Chip Size ◽  
Noise Amplifier ◽  
Stage Matching

Abstract Based on CMOS process, a low noise amplifier(LNA) operating at 7.4GHz~11.4GHz was designed. The two-stage differential cascode structure is adopted. Transformer was used to achieve inter-stage matching. Balun was used to achieve input and output matching, which reduces the number of inductors used, effectively reduces the chip size while ensuring good gain and noise figure. The actual measurement results show that the power gain at the center frequency of 9.4GHz is 27dB, the maximum noise figure is less than 3.82dB, the output power 1dB compression point is greater than 8dBm, the chip area is only 0.41mm×0.83mm(excluding PAD).

A Low Power SiGe-BiCMOS LNA for COMPASS Applications

2014 ◽  
Vol 513-517 ◽  
pp. 4580-4584
Author(s):  
Bing Liang Yu ◽  
Jin Li ◽  
Wen Yuan Li
Keyword(s):  
Low Power ◽  
Power Supply ◽  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Power Gain ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
Resistive Feedback ◽  
Noise Amplifier

A novel low-noise amplifier (LNA) suitable for COMPASS receiver applications is designed in SiGe-BiCMOS technology. Inductively degenerated technique and resistive feedback technique are employed to reduce the noise figure. With 1.8V power supply, the measured results achieve 17.23dB power gain and 2.58dB noise figure at 1.561GHz.

scholarly journals Design, simulation and optimization of a single stage Low Noise Amplifier (LNA) for very low power L- Band satellite handheld applications

2018 ◽  
Vol 17 (2) ◽  
pp. 37-42
Author(s):  
Mohammad Mohiuddin Uzzal
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Single Stage ◽  
Center Frequency ◽  
Simulation And Optimization ◽  
Consumption Cost ◽  
Design Systems ◽  
L Band ◽  
Noise Amplifier

In first stage of each microwave receiver, there is a Low Noise Amplifier (LNA) stage, and this LNA plays an important role to determine the quality factor of the receiver. The design of a LNA requires the trade-off of many important parameters including gain, Noise Figure (NF), stability, power consumption, cost and design complexity. In this paper, we have designed and simulate a single stage stable LNA circuit having gain 11.78 dB and noise figure 1.86 dB using microwave BJT AT3103 with Agilent package Advance Design Systems (ADS). This LNA operates at center frequency of 2 GHZ and it can be used in L-Band satellite modem for tracking applications.

scholarly journals A Low-Noise Amplifier Utilizing Current-Reuse Technique and Active Shunt Feedback for MedRadio Band Applications

2020 ◽  
pp. 306-316
Author(s):  
Mutanizam Abdul Mubin ◽  
◽  
Arjuna Marzuki
Keyword(s):  
Low Power ◽  
Return Loss ◽  
Noise Figure ◽  
High Gain ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Common Source ◽  
Cmos Process ◽  
Current Reuse ◽  
Noise Amplifier

In this work, a low-power 0.18-μm CMOS low-noise amplifier (LNA) for MedRadio applications has been designed and verified. Cadence IC5 software with Silterra’s C18G CMOS Process Design Kit were used for all design and simulation work. This LNA utilizes complementary common-source current-reuse topology and subthreshold biasing to achieve low-power operation with simultaneous high gain and low noise figure. An active shunt feedback circuit is used as input matching network to provide a suitable input return loss. For test and measurement purpose, an output buffer was designed and integrated with this LNA. Inductorless design approach of this LNA, together with the use of MOSCAPs as capacitors, help to minimize the die size. On post-layout simulations with LNA die area of 0.06 mm2 and simulated total DC power consumption of 0.5 mW, all targeted specifications are met. The simulated gain, input return loss and noise figure of this LNA are 16.3 dB, 10.1 dB and 4.9 dB respectively throughout the MedRadio frequency range. For linearity, the simulated input-referred P1dB of this LNA is -26.7 dBm while its simulated IIP3 is -18.6 dBm. Overall, the post-layout simulated performance of this proposed LNA is fairly comparable to some current state-of-the-art LNAs for MedRadio applications. The small die area of this proposed LNA is a significant improvement in comparison to those of the previously reported MedRadio LNAs.

A 79GHz Adaptive Gain Low Noise Amplifier for Radar Receivers

2018 ◽  
Vol 7 (2.24) ◽  
pp. 227
Author(s):  
J Manjula ◽  
A Ruhan Bevi
Keyword(s):  
Reflection Coefficient ◽  
Noise Figure ◽  
Cmos Technology ◽  
Input Power ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Center Frequency ◽  
Common Source ◽  
Adaptive Biasing ◽  
Noise Amplifier

This paper presents an Adaptive Gain 79GHz Low Noise Amplifier (LNA) suitable for Radars applications. The circuit schematic is a two stage LNA consists of Differential cascode configuration followed by a simple common source amplifier with an Adaptive Biasing (ADB) circuit. Adaptive biasing is a three- stage common source amplifier to decrease output voltage as input power increases. The circuit is simulated in 180nm CMOS technology and the simulation results have proved that the circuit operates at the center frequency 79GHz with adaptive biasing for adaptive gain. The gain analysis shows a decrease of 35-30dB with an increase in input power -50 to 0 dB. At 79GHz the circuit has achieved the input reflection coefficient (S11) of -24.7dB, reverse isolation (S12) of -3 dB, forward transmission coefficient (S21) of -2.97dB and output reflection coefficient (S22) of -5.62 dB with the reduced noise figure of 0.9 dB and a power consumption of 236 mW.  

243 GHz low-noise amplifier MMICs and modules based on metamorphic HEMT technology

2014 ◽  
Vol 6 (3-4) ◽  
pp. 215-223 ◽  
Author(s):  
Axel Tessmann ◽  
Volker Hurm ◽  
Arnulf Leuther ◽  
Hermann Massler ◽  
Rainer Weber ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Noise Figure ◽  
Coplanar Waveguide ◽  
High Electron Mobility Transistors ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
High Electron ◽  
Monolithic Integrated Circuit ◽  
Electron Mobility Transistors ◽  
Noise Amplifier

Two compact H-band (220–325 GHz) low-noise millimeter-wave monolithic integrated circuit (MMIC) amplifiers have been developed, based on a grounded coplanar waveguide (GCPW) technology utilizing 50 and 35 nm metamorphic high electron mobility transistors (mHEMTs). For low-loss packaging of the circuits, a set of waveguide-to-microstrip transitions has been realized on 50-μm-thick GaAs substrates demonstrating an insertion loss of <0.5 dB at 243 GHz. By applying the 50 nm gate-length process, a four-stage cascode amplifier module achieved a small-signal gain of 30.6 dB at 243 GHz and more than 28 dB in the bandwidth from 218 to 280 GHz. A second amplifier module, based on the 35-nm mHEMT technology, demonstrated a considerably improved gain of 34.6 dB at 243 GHz and more than 32 dB between 210 and 280 GHz. At the operating frequency, the two broadband low-noise amplifier modules achieved a room temperature noise figure of 5.6 dB (50 nm) and 5.0 dB (35 nm), respectively.

Sign in / Sign up

Export Citation Format

Share Document