scholarly journals A five-level multilevel topology utilizing multicarrier modulation technique

2019 ◽  
Vol 10 (2) ◽  
pp. 868
Author(s):  
Rabiya Rasheed ◽  
Saju K K ◽  
Bindu V
Keyword(s):  
Output Voltage ◽  
Multicarrier Modulation ◽  
Multilevel Inverter ◽  
Experimental Results ◽  
Modulation Technique ◽  
Capacitive Divider ◽  
Power Switches ◽  
Antiparallel Diodes ◽  
Harmonic Distortions

<p>This paper presents a new topology for cascaded H-bridge multilevel inverter utilizing multicarrier modulation technique. The new five-level topology utilizes a capacitive divider network consisting of two capacitors for producing output voltage levels. The developed circuit has reduced number of switches and dc sources compared to conventional five level inverters. Five main power switches, a single additional diode apart from antiparallel diodes, two capacitors and a dc supply constitute a single five level unit. Simulations as well as experimental results are verified for the new topology utilising multicarrier modulation technique with reduced harmonic distortions in the output.</p>

scholarly journals A novel simulated multilevel inverter topolo-gy with minimal switches

2017 ◽  
Vol 7 (1.2) ◽  
pp. 205
Author(s):  
R. Anand ◽  
S. Muthu Balaji
Keyword(s):  
Output Voltage ◽  
Multilevel Inverter ◽  
Experimental Results ◽  
New Technique ◽  
Multilevel Inverters ◽  
Maximum Charge ◽  
Power Switches

In this project, an advanced design of simulated multilevel inverters is proposed, which helps to boost the number of output voltage levels and decrease the number of power switches, driver circuits, and the maximum charge of the inverter. It is significant to note down advanced design, the unidirectional power switches are used. Results in decreased complexity and economical. The comparison is done with the conventional topologies and confirmed by simulation outcome. The planned design by using the new technique in produce all voltage levels for a stage inverter which its performance and functional accuracy is confirmed by simulation and experimental results.

Novel Symmetric and Asymmetric Multilevel Inverter Topology for Permanent Magnet Synchronous Motor

2017 ◽  
Vol 8 (3) ◽  
pp. 1002
Author(s):  
Aparna Prayag ◽  
Sanjay Bodkhe
Keyword(s):  
Permanent Magnet ◽  
Output Voltage ◽  
High Performance ◽  
Induction Motors ◽  
Permanent Magnet Synchronous Motor ◽  
Multilevel Inverter ◽  
Permanent Magnet Synchronous Motors ◽  
Asymmetric Mode ◽  
Power Switches ◽  
Inverter Topology

In this paper a new, simple multilevel inverter topology is proposed. Multilevel inverter uses several dc sources and power switches to synthesize desired output voltage waveform. The single phase structure of proposed topology in this paper consists of two dc sources and eight power switches. When the magnitudes of dc sources are equal it operates in symmetric mode, however in order to increase output voltage levels unequal magnitudes of dc sources are selected, then it operates in asymmetric mode. So far, multilevel inverter topologies have been used in motor drive industry to run induction motors. Recently permanent magnet synchronous motors (PMSM) are replacing induction motors.  Multilevel inverter is an attracting choice for driving high performance PMSM. However very few studies discuss the performance of multilevel inverter fed PMSM. In this paper simulation of novel symmetric and asymmetric multilevel inverter is carried out to analyze performance of PMSM. The topology is investigated through computer simulation using MATLAB/Simulink.

scholarly journals Novel Basic Block of Multilevel Inverter Using Reduced Number of On-State Switches and Cascaded Circuit Topology

2017 ◽  
Vol 2017 ◽  
pp. 1-16 ◽  
Author(s):  
Aparna Prayag ◽  
Sanjay Bodkhe
Keyword(s):  
Computer Simulation ◽  
Output Voltage ◽  
Multilevel Inverter ◽  
Basic Block ◽  
Matlab Simulink ◽  
Dc Voltage ◽  
Operating Modes ◽  
Power Switches ◽  
In Series ◽  
Basic Blocks

In this paper a basic block of novel topology of multilevel inverter is proposed. The proposed approach significantly requires reduced number of dc voltage sources and power switches to attain maximum number of output voltage levels. By connecting basic blocks in series a cascaded multilevel topology is developed. Each block itself is also a multilevel inverter. Analysis of proposed topology is carried out in symmetric as well as asymmetric operating modes. The topology is investigated through computer simulation using MATLAB/Simulink and validated experimentally on prototype in the laboratory.

scholarly journals Implementation of 5-Level H-Bridge Inverter with Multicarrier based Modulation Techniques

2020 ◽  
Vol 8 (5) ◽  
pp. 5180-5185
Keyword(s):  
Pulse Width ◽  
Output Voltage ◽  
Pulse Width Modulation ◽  
Reference Signal ◽  
Low Frequency ◽  
Harmonic Spectrum ◽  
Multilevel Inverter ◽  
Modulation Method ◽  
Dc Voltage ◽  
Modulation Technique

Paper Setup must be in A4 size with Margin: Top In the present paper multi carrier sinusoidal modulation technique which is an efficient method of producing control signals is used for a symmetrical inverter with several levels in cascade H Bridge is discussed. The Cascaded H-Bridge performance output levels depend on the DC voltage sources used at the input side. With the help of two DC voltage sources, five level output can be obtained whereas three sources gives levels of seven in output voltage. In this paper, multi-carrier SPWM switching is obtained for switching of multilevel inverter based switches. Two signals are used in this switching method, among which one of the signals is reference which is a low frequency sinusoidal signal and the one is a carrier signal. In case of sinusoidal PWM method of modulation technique, the reference signal is a sinusoidal one and triangular signal can be used as a carrier signal. These types of inverters have the ability to generate inverted output voltage with an efficient harmonic spectrum and reliable output results. This document provides switching signal for H-bridge inverter structure which can improve harmonic performance. The 5-level multilevel inverter is simulated for traditional carrier-based pulse-width modulation (PWM) phase change carrier techniques. The total harmonic performance of the output voltages is analyzed for the two PWM control methods. The performance of the symmetrical PWM CHB is simulated using MATLAB-SIMULINK model. Model results show that THD can be minimized to a limit with level shifted modulation method of the sinusoidal pulse width. The results from the simulations show that the quality of the waveform of the output voltage improves with less loss and with a lower THD.

New 8-Level Basic Structure for Cascaded Multilevel Inverters with Reduced Number of Switches and DC Voltage Sources

2019 ◽  
Vol 28 (03) ◽  
pp. 1950038 ◽  
Author(s):  
Ebrahim Babaei ◽  
Concettina Buccella ◽  
Carlo Cecati
Keyword(s):  
High Power ◽  
Output Voltage ◽  
Basic Structure ◽  
Experimental Results ◽  
Correct Operation ◽  
Dc Voltage ◽  
Medium Voltage ◽  
Multilevel Inverters ◽  
Power Switches

Multilevel inverters are generally used in medium-voltage and high-power applications. In this paper, a new 8-level basic structure for cascaded multilevel inverters is proposed. Based on proposed basic structure, two different cascaded multilevel topologies are proposed. The proposed cascaded multilevel inverters use less number of power switches, IGBTs and dc voltage sources compared with the conventional multilevel inverters. In order to generate all steps at the output voltage, three different algorithms to determine the amplitudes of dc voltage sources are presented. To reconfirm the performance and correct operation of the proposed topologies, the experimental results for a 15-level inverter are presented.

scholarly journals Design and Analsyis of 31-Level Asymmetric Cascaded H-Bridge Multilevel Inverter with Reduced Number of Switches

2020 ◽  
Vol 2 (2) ◽  
pp. 14-28
Author(s):  
Manoranjan A ◽  
Christober Asir Rajan C
Keyword(s):  
Multilevel Inverter ◽  
Modes Of Operation ◽  
Dc Voltage ◽  
Modulation Technique ◽  
Switching Losses ◽  
Power Switches ◽  
Low Order

A new multilevel inverter with less no of power switches is proposed. This is based on cascaded H-bridge topology. The design and analysis of 31-level reduced switch inverter with different modes of operation are presented in this paper. The proposed inverter is asymmetric in nature and it uses unequal DC voltage sources. PD-PWM modulation technique has been used here to get proper switching. The proposed idea has been validated through simulation and the received results provides better efficiency, less low order harmonics and less switching losses.

MULTI-WINDING TRANSFORMER-BASED DIODE CLAMPING MULTILEVEL INVERTER, EXPERIMENTAL RESULTS

2013 ◽  
Vol 22 (08) ◽  
pp. 1350071 ◽  
Author(s):  
EHSAN ESFANDIARI ◽  
FARHAD MESRINEJAD ◽  
NORMAN BIN MARIUN
Keyword(s):  
Output Voltage ◽  
Multilevel Inverter ◽  
Experimental Results ◽  
Peak Efficiency ◽  
Ability To Act

The feasibility of a staircase-output, diode clamping multilevel inverter based on multiwinding transformer is investigated through experimental results including: output voltage and current waveforms under resistive and inductive loads and the THD. The 2.5 kW, 7-level prototype of the constructed configuration proves the ability to act as an inverter under resistive and inductive loads and generates outputs with 2.1–11.5% of THD and 92.5% of peak efficiency. At last, a table of comparison with the closest topology is brought.

New Topology for Asymmetrical Multilevel Inverter: An Effort to Reduced Device Count

2017 ◽  
Vol 27 (04) ◽  
pp. 1850055 ◽  
Author(s):  
Kishor Thakre ◽  
Kanungo Barada Mohanty ◽  
Vinaya Sagar Kommukuri ◽  
Aditi Chatterjee
Keyword(s):  
Output Voltage ◽  
Pulse Width Modulation ◽  
Harmonic Distortion ◽  
Multilevel Inverter ◽  
Dc Voltage ◽  
Experimental Implementation ◽  
Voltage Stress ◽  
Power Switches ◽  
Driver Circuit ◽  
Gate Driver

Nowadays, multilevel inverters (MLI) are receiving remarkable attention due to salient features like less voltage stress on switches and low total harmonic distortion (THD) in output voltage. However, the required switch count increases with number of voltage levels. This paper presents a new topology for asymmetric multilevel inverter as a fundamental block. Each block generates 13-level output voltage using eight switches and four unequal dc voltage sources. The proposed configuration offers special features such as reduced number of switches, isolated dc sources, cost economy, less complex and modular structure than other similar contemporary topologies. Moreover, significant reduction in voltage stress on the circuit switches can be achieved. Comparative studies of proposed topology with the conventional and recent topologies have been presented in terms of power switches, gate driver circuit requirement, isolated dc voltage sources and total standing voltage. Multicarrier-based sinusoidal pulse width modulation (SPWM) scheme is adopted for generating switching signals using dSPACE real-time controller. In addition, proposed topology offers a fewer number of ON-state switches that lead to reduction in power loss. The proposed topology is validated through simulation and experimental implementation.

Transistor Clamped H-Bridge Five-Level Multilevel Inverter for Photovoltaic Application – A Hardware Prototype Implementation Using Inverted Double Reference Single Carrier PWM Technique

2017 ◽  
Author(s):  
Mahajan Sagar Bhaskar ◽  
Sanjeevikumar Padmanaban ◽  
Frede Blaabjerg ◽  
Anzari Mohammed
Keyword(s):  
Output Voltage ◽  
Pulse Width Modulation ◽  
Electronic System ◽  
Harmonic Spectrum ◽  
Multilevel Inverter ◽  
Multilevel Inverters ◽  
Single Carrier ◽  
Photovoltaic Application ◽  
Power Switches ◽  
Small Voltage

Inverters are Power Electronic System (PES) and proficient to converting Direct Currents (DC) into Alternating Currents (AC). Conventional two-level inverter has drawbacks like high Total Harmonic Distortions (THD), high voltage across power switch, high dv/dt of output voltage and electromagnetic interferences. Multilevel Inverters (MLIs) are employed to overcome the drawbacks of conventional two-level inverter. Multilevel Inverters generate an AC voltage using small voltage steps obtained with the help of DC supplies or capacitor banks. This paper deals with the implementation of a Transistor Clamped H-Bridge Multilevel Inverter (TCHB-MLI) using Inverted Double Reference Single Carrier Pulse Width Modulation (IDRSCPWM) technique for photovoltaic application. The proposed TCHB-MLI requires less number of power switches and drivers to achieve maximum number of output level. The analysis of the multilevel inverter output is done in terms of its harmonic spectrum, output voltage and output current for modulation indices 0.85, 1 and 1.25. The control signals for the power switches of the proposed TCHB-MLI are developed by using SPARTAN 3E-XCS250E trainer kit. Experimental results will verify the functionality, design of the proposed TCHB-MLI and IDRSCPWM Technique.

A Symmetrical Multilevel Inverter Topology with Minimal Switch Count and Total Harmonic Distortion

2020 ◽  
Vol 29 (11) ◽  
pp. 2050174 ◽  
Author(s):  
Kavali Janardhan ◽  
Arvind Mittal ◽  
Amit Ojha
Keyword(s):  
Output Voltage ◽  
Pulse Width Modulation ◽  
Harmonic Distortion ◽  
Multilevel Inverter ◽  
Total Harmonic Distortion ◽  
Lookup Table ◽  
Control Technique ◽  
Power Switches ◽  
Dspace 1104 ◽  
Working Principle

A multilevel inverter (MLI) with reduced number of power devices, especially for the higher output levels, is presented in this paper. The generalized topology for ([Formula: see text]) level MLI is developed with symmetrical isolated dc sources and ([Formula: see text]) number of switches. A five-level MLI is developed with five power switches and then by adding each one additional switch two more levels are added in the output voltage waveform. With the help of lookup table, the working principle of the proposed five-level MLI topology is explained. Sinusoidal pulse width modulation–phase disposition control technique has been used to get a minimal total harmonic distortion (THD). The proposed MLI topology is simulated on the MATLAB platform. The laboratory prototype is developed for five-level MLI, and the experimental results obtained validate the simulation studies. The dSPACE 1104 is used for generating gate pulses in case of experimentation. The output voltage and current THDs obtained are 9.20% and 4.60%, respectively; the harmonics are mitigated more with five-level inverter. The proposed topology is compared with the cascaded H-bridge multilevel inverter.

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