scholarly journals Novel Basic Block of Multilevel Inverter Using Reduced Number of On-State Switches and Cascaded Circuit Topology

2017 ◽  
Vol 2017 ◽  
pp. 1-16 ◽  
Author(s):  
Aparna Prayag ◽  
Sanjay Bodkhe

In this paper a basic block of novel topology of multilevel inverter is proposed. The proposed approach significantly requires reduced number of dc voltage sources and power switches to attain maximum number of output voltage levels. By connecting basic blocks in series a cascaded multilevel topology is developed. Each block itself is also a multilevel inverter. Analysis of proposed topology is carried out in symmetric as well as asymmetric operating modes. The topology is investigated through computer simulation using MATLAB/Simulink and validated experimentally on prototype in the laboratory.

10.29007/m2mq ◽  
2018 ◽  
Author(s):  
Shubham R. Patel ◽  
Gaurang K. Sharma ◽  
Ashish R. Patel

Multilevel inverter allows the production of high voltage with lower harmonic distortion in ac output and it eliminates the need of transformer. With the usage of multilevel inverter, we can get the required ac voltage output from multiple dc voltage rails. One of the disadvantage in it is the unbalancing of dc link capacitor voltage. The basic aim of this paper is the balancing of dc link capacitor voltage in diode-clamped multilevel inverter. There are different approaches which could be used for balancing of the capacitor voltage. In this paper, the method of additional auxiliary circuit in the form of Two-level Boost converter is being adopted to balance the inner capacitor voltages so as to get the required multilevel output. This balancing leads to the reliability in the inverter output voltage and extension in life of capacitor. The simulations for this are being performed in MATLAB SIMULINK® and the result are being analyzed for the same by employing it for different load condition. The scheme thus offer the proper balancing of capacitor voltage.


2019 ◽  
Vol 16 (1) ◽  
pp. 18 ◽  
Author(s):  
Thiyagarajan V ◽  
Somasundaran P

Multilevel inverter plays an important role in the field of modern power electronics and is widely being used for many high voltage and high power industrial and commercial applications. The objective of this paper is to design and simulate the modified asymmetric multilevel inverter topology with reduced number of switches. The proposed inverter topology synthesizes 21-level output voltage during symmetric operation using three DC voltage sources and twelve switches 8 main switches and 4 auxiliary switches. The different methods of calculating the switching angles are presented in this paper. The MATLAB/Simulink software is used to simulate the proposed inverter. The performance of the proposed inverter is analyzed and the corresponding simulation results are presented in this paper.


2017 ◽  
Vol 27 (04) ◽  
pp. 1850055 ◽  
Author(s):  
Kishor Thakre ◽  
Kanungo Barada Mohanty ◽  
Vinaya Sagar Kommukuri ◽  
Aditi Chatterjee

Nowadays, multilevel inverters (MLI) are receiving remarkable attention due to salient features like less voltage stress on switches and low total harmonic distortion (THD) in output voltage. However, the required switch count increases with number of voltage levels. This paper presents a new topology for asymmetric multilevel inverter as a fundamental block. Each block generates 13-level output voltage using eight switches and four unequal dc voltage sources. The proposed configuration offers special features such as reduced number of switches, isolated dc sources, cost economy, less complex and modular structure than other similar contemporary topologies. Moreover, significant reduction in voltage stress on the circuit switches can be achieved. Comparative studies of proposed topology with the conventional and recent topologies have been presented in terms of power switches, gate driver circuit requirement, isolated dc voltage sources and total standing voltage. Multicarrier-based sinusoidal pulse width modulation (SPWM) scheme is adopted for generating switching signals using dSPACE real-time controller. In addition, proposed topology offers a fewer number of ON-state switches that lead to reduction in power loss. The proposed topology is validated through simulation and experimental implementation.


Energies ◽  
2019 ◽  
Vol 12 (6) ◽  
pp. 977 ◽  
Author(s):  
Hussain Bassi ◽  
Zainal Salam

In this paper, a new single-phase hybrid multilevel inverter (MLI) is proposed. Compared to other existing MLI topologies, the proposed circuit is capable of producing a higher number of output voltage levels using fewer power switches and dc sources. The levels are synthesized by switching the dc voltage sources in series/parallel combinations. An auxiliary circuit is introduced to double the number of levels by creating an intermediate step in between two levels. In addition, a zero level is introduced to overcome the inherent absence of this level in the original circuit. To improve the total harmonic distortion, a hybrid modulation technique is utilized. The operation and performance of the circuit are analyzed and confirmed using MATLAB/Simulink simulation. To validate the workability of the proposed idea, a 300 W, a thirteen level MLI (including the zero level) is designed and constructed. The circuit is tested with a no-load, resistive load and resistive-inductive load. The experimental results match very closely with the simulation and mathematical analysis.


2008 ◽  
Vol 128 (3) ◽  
pp. 244-250
Author(s):  
Kenji Amei ◽  
Kenji Teshima ◽  
Youhei Tanizaki ◽  
Takahisa Ohji ◽  
Masaaki Sakui

Author(s):  
Chinnapettai Ramalingam Balamurugan ◽  
S.P. Natarajan ◽  
T.S. Anandhi

The multi level inverter system is habitually exploited in AC drives, when both reduced harmonic contents and high power are required. In this paper, a new topology for three phase asymmetrical multilevel inverter employing reduced number of switches is introduced. With less number of switches, the cost, space and weight of the circuit are automatically reduced. This paper discusses the new topology, the switching strategies and the operational principles of the chosen inverter. Simulation is carried out using MATLAB-SIMULINK. Various conventional PWM techniques that are appropriate to the chosen circuit such as PDPWM, PODPWM, APODPWM, VFPWM and COPWM are employed in this work. COPWM technique affords the less THD value and also affords a higher fundamental RMS output voltage.


Author(s):  
Aparna Prayag ◽  
Sanjay Bodkhe

In this paper a new, simple multilevel inverter topology is proposed. Multilevel inverter uses several dc sources and power switches to synthesize desired output voltage waveform. The single phase structure of proposed topology in this paper consists of two dc sources and eight power switches. When the magnitudes of dc sources are equal it operates in symmetric mode, however in order to increase output voltage levels unequal magnitudes of dc sources are selected, then it operates in asymmetric mode. So far, multilevel inverter topologies have been used in motor drive industry to run induction motors. Recently permanent magnet synchronous motors (PMSM) are replacing induction motors.  Multilevel inverter is an attracting choice for driving high performance PMSM. However very few studies discuss the performance of multilevel inverter fed PMSM. In this paper simulation of novel symmetric and asymmetric multilevel inverter is carried out to analyze performance of PMSM. The topology is investigated through computer simulation using MATLAB/Simulink.


Energies ◽  
2019 ◽  
Vol 12 (3) ◽  
pp. 394 ◽  
Author(s):  
Dai-Van Vo ◽  
Minh-Khai Nguyen ◽  
Duc-Tri Do ◽  
Youn-Ok Choi

A novel single-phase nine-level boost inverter is proposed in this paper. The proposed inverter has an output voltage which is higher than the input voltage by switching capacitors in series and in parallel. The maximum output voltage of the proposed inverter is determined by using the boost converter circuit, which has been integrated into the circuit. The proposed topology is able to invert the multilevel voltage with the high step-up output voltage, simple structure and fewer power switches. In this paper, the circuit configuration, the operating principle, and the output voltage expression have been derived. The proposed converter has been verified by simulation and experiment with the help of PSIM software and a laboratory prototype. The experimental results match the theoretical calculation and the simulation results.


2019 ◽  
Vol 29 (01) ◽  
pp. 2050004
Author(s):  
Sidharth Sabyasachi ◽  
Vijay B. Borghate ◽  
Santosh Kumar Maddugari

This paper presents a module for single-phase multilevel inverter topology. The proposed module generates maximum 21-level bipolar output voltage with asymmetric sources without H-bridge. This results in reduction in filter cost and size. The module can be cascaded for high voltage applications. The same arrangement of voltage source magnitudes in first module is maintained in the remaining cascaded modules. The proposed topology is suitable for the applications like electric vehicle and emergency services like residences and hospitality industries, etc. A set of comparisons between the proposed and recently published topologies are provided to differentiate between them. The topology is simulated and verified in MATLAB/SIMULINK. A hardware prototype is developed in the laboratory for experimental confirmation with various conditions.


2010 ◽  
Vol 170 (3) ◽  
pp. 40-47
Author(s):  
Kenji Amei ◽  
Kenji Teshima ◽  
Youhei Tanizaki ◽  
Takahisa Ohji ◽  
Masaaki Sakui

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