Error elimination ECC by horizontal error detection and vertical-LDPC ECC to increase data-retention time by 230% and acceptable bit-error rate by 90% for 3D-NAND flash SSDs

2018 ◽  
Author(s):  
Shun Suzuki ◽  
Yoshiaki Deguchi ◽  
Toshiki Nakamura ◽  
Kyoji Mizoguchi ◽  
Ken Takeuchi
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
Error Detection ◽  
Retention Time ◽  
Nand Flash ◽  
Data Retention ◽  
Error Elimination

scholarly journals Fuzzy Based Adaptive Controller for on - Chip Communication

2018 ◽  
Vol 7 (3.27) ◽  
pp. 362
Author(s):  
M Jasmin ◽  
T Vigneswaran
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
Error Detection ◽  
Input Data ◽  
Fuzzy Controller ◽  
Proper Time ◽  
System On Chip ◽  
Coding Scheme ◽  
Error Detection And Correction ◽  
On Chip

Occurrence of bit error is more when communication takes place in System on chip environment. By employing proper error detection and correction codes the bit error rate can be considerably reduced in On-chip communication. As System on chip involves heterogeneous system the efficiency of communication is improved when reconfigurable multiple coding schemes are preferred. Depending upon the requirements for various subsystem the correct code has to be selected. Due to the variations in input demands based on various subsystems the proper selection of codes become fuzzy in nature. In this paper Fuzzy Controller is designed to select the correct coding scheme. Inputs are given to the fuzzy controller based on the application demand of the user. The input parameters are minimum bit error rate, computational complexity and correlation level of the input data. Fuzzy Controller employs three membership functions and 27 rules to select the appropriate coding scheme. The selected coding scheme should be communicated at the proper time to the decoder. To enable the decoding process selected coding scheme is communicated effectively by using less overhead frame format. To verify the functionality of fuzzy controller random input data sets are used for testing.  

scholarly journals Error Detection in Turbo Decoding using Neural Network

2019 ◽  
Vol 9 (1S) ◽  
pp. 218-221
Keyword(s):  
Neural Network ◽  
Bit Error Rate ◽  
Error Rate ◽  
Error Detection ◽  
Turbo Codes ◽  
Iterative Decoding ◽  
Turbo Decoding ◽  
Turbo Decoder ◽  
The Neural Network ◽  
Turbo Encoder

In this paper reduction of errors in turbo decoding is done using neural network. Turbo codes was one of the first thriving attempt for obtaining error correcting performance in the vicinity of the theoretical Shannon bound of –1.6 db. Parallel concatenated encoding and iterative decoding are the two techniques available for constructing turbo codes. Decrease in Eb/No necessary to get a desired bit-error rate (BER) is achieved for every iteration in turbo decoding. But the improvement in Eb/No decreases for each iteration. From the turbo encoder, the output is taken and this is added with noise, when transmitting through the channel. The noisy data is fed as an input to the neural network. The neural network is trained for getting the desired target. The desired target is the encoded data. The turbo decoder decodes the output of neural network. The neural network help to reduce the number of errors. Bit error rate of turbo decoder trained using neural network is less than the bit error rate of turbo decoder without training.

On Die Bit Error Rate Estimator for NAND Flash Memory

2017 ◽  
Vol 64 (7) ◽  
pp. 772-776 ◽  
Author(s):  
Mustafa N. Kaynak ◽  
Patrick R. Khayat ◽  
Sivagnanam Parthasarathy
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
Flash Memory ◽  
Nand Flash ◽  
Nand Flash Memory

scholarly journals A Low-Cost Improved Method of Raw Bit Error Rate Estimation for NAND Flash Memory of High Storage Density

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1900
Author(s):  
Kainan Ma ◽  
Ming Liu ◽  
Tao Li ◽  
Yibo Yin ◽  
Hongda Chen
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
Flash Memory ◽  
Low Cost ◽  
Estimation Method ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Storage Density ◽  
Raw Bit Error Rate ◽  
High Storage

Cells wear fast in NAND flash memory of high storage density (HSD), so it is very necessary to have a long-term frequent in-time monitoring on its raw bit error rate (RBER) changes through a fast RBER estimation method. As the flash of HSD already has relatively lower reading speed, the method should not further degrade its read performance. This paper proposes an improved estimation method utilizing known data comparison, includes interleaving to balance the uneven error distribution in the flash of HSD, a fast RBER estimation module to make the estimated RBER highly linearly correlated with the actual RBER, and enhancement strategies to accelerate the decoding convergence of low-density parity-check (LDPC) codes and thereby make up the rate penalty caused by the known data. Experimental results show that when RBER is close to the upper bound of LDPC code, the reading efficiency can be increased by 35.8% compared to the case of no rate penalty. The proposed method only occupies 0.039mm2 at 40nm process condition. Hence, the fast, read-performance-improving, and low-cost method is of great application potential on RBER monitoring in the flash of HSD.

scholarly journals Improvement in bit-error rate for optoelectronic multicomputer interconnection networks using cyclic redundancy code error detection

1997 ◽  
Vol 9 (6) ◽  
pp. 848-850 ◽  
Author(s):  
P. May ◽  
J. Cross ◽  
A. Lopez-Lagunas ◽  
B. Buchanan ◽  
D.S. Wills ◽  
...  
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
Error Detection ◽  
Interconnection Networks
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