Current Status of Ferroelectric Random-Access Memory

MRS Bulletin ◽  
2004 ◽  
Vol 29 (11) ◽  
pp. 823-828 ◽  
Author(s):  
Yoshihiro Arimoto ◽  
Hiroshi Ishiwara
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Current Status ◽  
Access Time ◽  
Access Memory ◽  
Ferroelectric Random Access Memory ◽  
The Status ◽  
Recent Developments ◽  
Static Ram ◽  
Ferroelectric Capacitors

AbstractThe current status of ferroelectric random-access memory (FeRAM) technology is reviewed in this article. Presented first is the status of conventional FeRAM, in which the memory cells are composed of ferroelectric capacitors to store the data and cell-selection transistors to access the selected capacitors. Discussed next are recent developments in the field. Pb(Zrx, Ti1–x)O3 (PZT) and SrBi2Ta2O9 (SBT) films are being used to produce 0.13 mμ and 0.18 μm FeRAM cells, respectively, with a stacked capacitor configuration; these cells are easily embedded into logic circuits. A new class of FeRAM called 6T4C—containing static RAM (SRAM) cells composed of six transistors (6T) and four ferroelectric capacitors (4C)—has been commercially produced. This type of FeRAM features a nondestructive readout operation, unlimited read/write cycling, and a fast access time of less than 10 ns. Lastly, the status of field-effect-transistor (FET)-type FeRAM is reviewed, emphasizing that the data retention time of a ferroelectric-gate FET has been improved to more than a month in recent studies.

Characterization of Polarization Switching Behavior of Pt/SrBi2Ta2O9/Pt Ferroelectric Capacitors in Ferroelectric Random Access Memory

2002 ◽  
Vol 41 (Part 1, No. 2A) ◽  
pp. 694-697 ◽  
Author(s):  
Young Min Kang ◽  
Choong Heui Chung ◽  
Sang Hyun Oh ◽  
Beelyong Yang ◽  
Seaung Suk Lee ◽  
...  
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Polarization Switching ◽  
Switching Behavior ◽  
Access Memory ◽  
Ferroelectric Random Access Memory ◽  
Ferroelectric Capacitors

scholarly journals Pre-Emphasis Pulse Design for Random-Access Memory

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1454
Author(s):  
Yoshihiro Sugiura ◽  
Toru Tanzawa
Keyword(s):  
Time Constant ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Memory Access ◽  
Access Time ◽  
Access Memory ◽  
Delay Times ◽  
Cell Current ◽  
The Impact

This paper describes how one can reduce the memory access time with pre-emphasis (PE) pulses even in non-volatile random-access memory. Optimum PE pulse widths and resultant minimum word-line (WL) delay times are investigated as a function of column address. The impact of the process variation in the time constant of WL, the cell current, and the resistance of deciding path on optimum PE pulses are discussed. Optimum PE pulse widths and resultant minimum WL delay times are modeled with fitting curves as a function of column address of the accessed memory cell, which provides designers with the ability to set the optimum timing for WL and BL (bit-line) operations, reducing average memory access time.

Design of Low Power with Expanded Noise Margin Subthreshold 12T SRAM Cell for Ultra-Low Power Devices

2020 ◽  
pp. 2150106
Author(s):  
Harekrishna Kumar ◽  
V. K. Tomar
Keyword(s):  
Power Dissipation ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Access Time ◽  
Access Memory ◽  
Subthreshold Region ◽  
Noise Margin ◽  
Static Noise

In the proposed work, a differential write and single-ended read half-select free 12 transistors static random access memory cell is designed and simulated. The proposed cell has a considerable reduction in power dissipation with better stability and moderate performance. This cell operates in subthreshold region and has a higher value of read static noise margin as compared to conventional six transistors static random access memory cell. A power cut-off technique is utilized between access and pull-up transistors during the write operation. It results in an increase in write static noise margin as compared to all considered cells. In the proposed cell, read and write access time is improved along with a reduction in read/write power dissipation as compared to conventional six transistors static random access memory cell. The bitline leakage current in the proposed cell is reduced which improves the [Formula: see text] ratio of the cell under subthreshold region. The proposed cell occupies less area as compared to considered radiation-hardened design 12 transistors static random access memory cell. The computed electrical quality metric of proposed cell is better among considered static random access memory cells. Process variation analysis of read stability, access time, power dissipation, read current and leakage current has been performed with the help of Monte Carlo simulation at 3,000 points to get more soundness in the results. All characteristics of static random access memory cells are compared at various supply voltages.

scholarly journals Single-Event Effects in the Peripheral Circuitry of a Commercial Ferroelectric Random Access Memory

2018 ◽  
Vol 65 (8) ◽  
pp. 1708-1714 ◽  
Author(s):  
A. L. Bosser ◽  
V. Gupta ◽  
A. Javanainen ◽  
G. Tsiligiannis ◽  
S. D. LaLumondiere ◽  
...  
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Single Event ◽  
Access Memory ◽  
Single Event Effects ◽  
Ferroelectric Random Access Memory
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