Surface Defects and Passivation of Ge and III–V Interfaces

MRS Bulletin ◽  
2009 ◽  
Vol 34 (7) ◽  
pp. 504-513 ◽  
Author(s):  
Michel Houssa ◽  
Evgueni Chagarov ◽  
Andrew Kummel
Keyword(s):  
Integrated Circuits ◽  
First Principles ◽  
Surface Defects ◽  
Gate Dielectrics ◽  
High Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Circuits ◽  
Experimental Characterization ◽  
Metal Gates

AbstractThe need for high-κ gate dielectrics and metal gates in advanced integrated circuits has reopened the door to Ge and III–V compounds as potential replacements for silicon channels, offering the possibility to further increase the performances of complementary metal oxide semiconductor (CMOS) circuits, as well as adding new functionalities. Yet, a fundamental issue related to high-mobility channels in CMOS circuits is the electrical passivation of their interfaces (i.e., achieving a low density of interface defects) approaching state-of-the-art Si-based devices. Here we discuss promising approaches for the passivation of Ge and III–V compounds and highlight insights obtained by combining experimental characterization techniques with first-principles simulations.

scholarly journals Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Aryan Afzalian
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
High Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Grand Challenge ◽  
Gate Length ◽  
Delay Performance ◽  
Effect Transistor

AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

Analysis and Simulation of a Low-Leakage Analog Single Gate and FinFET Circuits

2014 ◽  
Vol 13 (02) ◽  
pp. 1450012 ◽  
Author(s):  
Manorama Chauhan ◽  
Ravindra Singh Kushwah ◽  
Pavan Shrivastava ◽  
Shyam Akashe
Keyword(s):  
Integrated Circuits ◽  
Metal Oxide ◽  
Low Power ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Short Channel ◽  
State Dependency ◽  
Low Leakage

In the world of Integrated Circuits, complementary metal–oxide–semiconductor (CMOS) has lost its ability during scaling beyond 50 nm. Scaling causes severe short channel effects (SCEs) which are difficult to suppress. FinFET devices undertake to replace usual Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) because of their better ability in controlling leakage and diminishing SCEs while delivering a strong drive current. In this paper, we present a relative examination of FinFET with the double gate MOSFET (DGMOSFET) and conventional bulk Si single gate MOSFET (SGMOSFET) by using Cadence Virtuoso simulation tool. Physics-based numerical two-dimensional simulation results for FinFET device, circuit power is presented, and classifying that FinFET technology is an ideal applicant for low power applications. Exclusive FinFET device features resulting from gate–gate coupling are conversed and efficiently exploited for optimal low leakage device design. Design trade-off for FinFET power and performance are suggested for low power and high performance applications. Whole power consumptions of static and dynamic circuits and latches for FinFET device, believing state dependency, show that leakage currents for FinFET circuits are reduced by a factor of over ~ 10X, compared to DGMOSFET and ~ 20X compared with SGMOSFET.

Experimental Basis and Design of a New Cochlear Prosthesis System

1987 ◽  
Vol 96 (1_suppl) ◽  
pp. 76-79
Author(s):  
J. Génin ◽  
R. Charachon
Keyword(s):  
Theoretical Model ◽  
Integrated Circuits ◽  
Cochlear Implant ◽  
Dynamic Range ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Semiconductor Technology ◽  
Experimental Basis ◽  
Cochlear Prosthesis

In a multichannel cochlear prosthesis, electrical interactions between electrodes impose severe limitations on dynamic range and selectivity. We present a theoretical model to cope with these limitations. Building a successful cochlear implant requires full custom-integrated circuits. We present the design of such a device, implemented in complementary metal oxide semiconductor technology. The area of the chip is 9 mm2 and it can stimulate 15 cochlear electrodes with current impulses.

Power-Delay Trade-Offs in Complementary Metal-Oxide Semiconductor Circuits Using Self and Optimum Bulk Control

2020 ◽  
Vol 18 (3) ◽  
pp. 210-215
Author(s):  
Shubham Tayal ◽  
Sunil Jadav
Keyword(s):  
Power Dissipation ◽  
Complementary Metal Oxide Semiconductor ◽  
Joint Effect ◽  
Sequential Circuits ◽  
Vlsi Circuits ◽  
Oxide Semiconductor ◽  
Cmos Circuits ◽  
Trade Offs ◽  
Self Bias ◽  
Semiconductor Circuits

Power dissipation and delay are the challenging issues in the design of VLSI circuits. This manuscript explores joint effect of Self-Bias transistors (SBTs) and Optimum Bulk Bias Technique (OBBT) on CMOS circuits. Earlier investigations on SBTs shows decrease in power dissipation of combinational as well as sequential circuits. We extend the analysis by studying the effect of OBBT on the static and dynamic power of CMOS circuits with SBTs coupled amid the pull-up/down network and the supply bars. Extensive SPICE simulations have been carried out in 0.18 μm technology. Results demonstrate that, a 73% drop in power in case of combinational circuits and 43% in case of sequential circuits can be accomplished by engaging OBBT in digital circuits. Trade-off between power and delay is also been presented.

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