Source and Drain Contacts for Germanium and III–V FETs for Digital Logic

The scaling of transistors to smaller dimensions and the exploration of devices with III–V and Ge channels for digital logic places serious demands on the ohmic contacts used in these devices. Contacts with extremely low specific contact resistances are required to take full advantage of the performance promised by alternative semiconductor materials. In addition, device processes and contact morphologies must be compatible with the geometry and feature sizes of the transistors. In this article, we begin by reviewing what is known about contacts to Ge, InGaAs, InAs, and InSb, including the role of Fermi level pinning on the Schottky barrier that is often formed at the metal/semiconductor interface and common strategies for forming ohmic contacts. Then we turn our attention to the additional challenges faced when preparing ohmic contacts for the many types of field-effect transistors now under development for Ge and III–V complementary field-effect transistor technology.