Ambipolar Thin-Film Transistors Fabricated by PECVD Nanocrystalline Silicon

2006 ◽  
Vol 910 ◽  
Author(s):  
Czang-Ho Lee ◽  
Andrei Sazonov ◽  
Mohammad R. E. Rad ◽  
G. Reza Chaji ◽  
Arokia Nathan
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Field Effect ◽  
Chemical Vapor ◽  
Hole Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Nanocrystalline Silicon ◽  
Oxide Semiconductor ◽  
Hole Injection ◽  
Current Ratio

AbstractWe report on directly deposited plasma-enhanced chemical vapor deposition (PECVD) nanocrystalline silicon (nc-Si:H) ambipolar thin-film transistors (TFTs) fabricated at 260 °C. The ambipolar operation is achieved adopting Cr metal contacts with high-quality nc-Si:H channel layer, which creates highly conductive Cr silicided drain/source contacts, reducing both electron and hole injection barriers. The n-channel nc-Si:H TFTs show a field-effect electron mobility (meFE) of 150 cm2/Vs, threshold voltage (VT) ~ 2 V, subthreshold slope (S) ~0.3 V/dec, and ON/OFF current ratio of more than 107, while the p-channel nc-Si:H TFTs show a field-effect hole mobility (mhFE) of 26 cm2/Vs, VT ~ -3.8 V, S ~0.25 V/dec, and ON/OFF current ratio of more than 106. Complementary metal-oxide-semiconductor (CMOS) logic integrated with two ambipolar nc-Si:H TFTs shows reasonable transfer characteristics. The results presented here demonstrate that low-temperature nc-Si:H TFT technology is feasible for total integration of active-matrix TFT backplanes.

Study of nanocrystalline silicon-germanium for the development of thin film transistors

2020 ◽  
Vol 89 (1) ◽  
pp. 10102 ◽  
Author(s):  
Arturo Torres ◽  
Mario Moreno ◽  
Pedro Rosales ◽  
Miguel Dominguez ◽  
Alfonso Torres ◽  
...  
Keyword(s):  
Thin Film ◽  
Silicon Germanium ◽  
Thin Film Transistors ◽  
Chemical Vapor ◽  
Nanocrystalline Silicon ◽  
Subthreshold Slope ◽  
Rf Power ◽  
Crystalline Fraction ◽  
Current Ratio ◽  
Active Layers

In this work, we study the effect of the deposition RF-power on the structural, optical and electrical properties of hydrogenated nanocrystalline silicon-germanium (nc-SiGe:H) thin films obtained by plasma enhanced chemical vapor deposition (PECVD) at substrate temperature of 200 °C. The objective is to produce films with high crystalline fraction in order to be used as active layers in thin film transistors (TFTs). Bottom-gate (BG) thin film transistors were fabricated with nc-SiGe:H active layers, deposited at different RF-power. Values of ON-OFF current ratio, subthreshold slope and threshold voltage of 105, 0.12 V/dec and 0.9 V, respectively, were obtained on TFTs with the nc-SiGe:H active layer deposited at 25 W.

scholarly journals Amorphous Hafnium-Indium-Zinc Oxide Semiconductor Thin Film Transistors

2012 ◽  
Vol 2012 ◽  
pp. 1-4 ◽  
Author(s):  
Sheng-Po Chang ◽  
San-Syong Shih
Keyword(s):  
Thin Film ◽  
Zinc Oxide ◽  
Thin Film Transistors ◽  
Oxide Semiconductor ◽  
Subthreshold Slope ◽  
Field Effect Mobility ◽  
Excellent Performance ◽  
Current Ratio ◽  
Indium Zinc Oxide ◽  
Sputtering Power

We reported on the performance and electrical properties of co-sputtering-processed amorphous hafnium-indium-zinc oxide (α-HfIZO) thin film transistors (TFTs). Co-sputtering-processedα-HfIZO thin films have shown an amorphous phase in nature. We could modulate the In, Hf, and Zn components by changing the co-sputtering power. Additionally, the chemical composition ofα-HfIZO had a significant effect on reliability, hysteresis, field-effect mobility (μFE), carrier concentration, and subthreshold swing (S) of the device. Our results indicated that we could successfully and easily fabricateα-HfIZO TFTs with excellent performance by the co-sputtering process. Co-sputtering-processedα-HfIZO TFTs were fabricated with an on/off current ratio of~106, higher mobility, and a subthreshold slope as steep as 0.55 V/dec.

Instability of OTFT with Organic Gate Dielectrics

2007 ◽  
Vol 124-126 ◽  
pp. 407-410
Author(s):  
Sang Chul Lim ◽  
Seong Hyun Kim ◽  
Gi Heon Kim ◽  
Jae Bon Koo ◽  
Jung Hun Lee ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Field Effect ◽  
Gate Dielectrics ◽  
Gate Insulator ◽  
Semiconductor Layer ◽  
Field Effect Mobility ◽  
Current Ratio ◽  
Dielectric Thickness ◽  
Inverter Circuit

We report the effects of instability with gate dielectrics of pentacene thin film transistors (OTFTs) inverter circuits. We used to the UV sensitive curable resin and poly-4-vinylphenol(PVP) by gate dielectrics. The inverter supply bias is VDD= -40 V. For a given dielectric thickness and applied voltage, pentacene OTFTs with inverter circuits measurements field effect mobility, on-off current ratio, Vth. The field effect mobility 0.03~0.07 cm2/Vs, and the threshold voltage is -3.3 V ~ -8.8 V. The on- and off-state currents ratio is about 103~106. From the OTFT device and inverter circuit measurement, we observed hysteresis behavior was caused by interface states of between the gate insulator and the pentacene semiconductor layer.

Thin Film Transistors on Plastic Substrates Using Silicon Deposited by Microwave ECR-CVD

2003 ◽  
Vol 769 ◽  
Author(s):  
Lihong Teng ◽  
Wayne A. Anderson
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Field Effect ◽  
Silicon Films ◽  
Subthreshold Swing ◽  
Field Effect Mobility ◽  
Current Ratio ◽  
Saturation Field ◽  
Plastic Substrates

AbstractThe properties of thin film transistors (TFT's) on plastic substrates with active silicon films deposited by microwave ECR-CVD were studied. Two types of plastic were used, PEEK and polyimide. The a-Si:H TFT deposited at 200°C on polyimide substrates showed a saturation field effect mobility of 4.5 cm2/V-s, a threshold voltage of 3.7 V, a subthreshold swing of 0.69 V/dec and an ON/OFF current ratio of 7.9×106, while the TFT fabricated on PEEK at 200°C showed a saturation field effect mobility of 3.9 cm2/V-s, a threshold voltage of 4.1 V, a subthreshold swing of 0.73 V/dec and an ON/OFF current ratio of 4×106. Comparison is made to TFT's with the Si deposited at 400°C on glass.

Hydrogen in Ultralow Temperature SiO2for Nanocrystalline Silicon Thin Film Transistors

2004 ◽  
Vol 814 ◽  
Author(s):  
Alex Kattamis ◽  
I-Chun Cheng ◽  
Steve Allen ◽  
Sigurd Wagner
Keyword(s):  
Thin Film ◽  
Leakage Current ◽  
Current Density ◽  
Thin Film Transistors ◽  
Secondary Ion Mass Spectrometry ◽  
Crystalline Silicon ◽  
Chemical Vapor ◽  
Nanocrystalline Silicon ◽  
Film Deposition ◽  
Silicon Thin Film

AbstractNanocrystalline silicon is a candidate material for fabricating thin film transistors with high carrier mobilities on plastic substrates. A major issue in the processing of nanocrystalline silicon thin film transistors (nc-Si:H TFTs) at ultralow temperatures is the quality of the SiO2gate dielectric. SiO2deposited at less than 250°C by radio frequency plasma enhanced chemical vapor deposition (rf-PECVD), and not annealed at high temperature after deposition, exhibits high leakage current and voltage shifts when incorporated into TFT's. Secondary ion mass spectrometry (SIMS) measurements show that the hydrogen concentration (NH) in PECVD oxide deposited at 150°C on crystalline silicon (x-Si) is ∼ 0.8 at. %. This is much higher than in thermal oxides on x-Si, which display concentrations of less than 0.003 at. %. The leakage current density for thermal oxides on x-Si at a bias of 10 V is ∼9×10−6A/cm2whereas for 200°C PECVD oxides on nc-Si:H the current is ∼1×10−4A/cm2. As the temperature of the SiO2deposition is reduced to 150°C the current density rises by up to two orders of magnitude more. The H which is suspected to cause the leakage current across the PECVD oxide originates from the nc-Si:H substrate and the SiH4source gas. We analyzed the 300-nm gate oxide in capacitor structures of Al / SiO2/n+nc-Si:H / Cr / glass, Al / SiO2/ n+nc-Si:H / x-Si, and Al / SiO2/ x-Si. Vacuum annealing the nc-Si:H prior to PECVD of the oxide drives H out of the nc-Si:H film and reduces the amount of H incorporated into the oxide that is deposited on top. SiO2film deposition from SiH4and N2O at high He dilution has a still greater effect on lowering NH. The leakage current at a 10 V bias dropped from ∼1×10−4A/cm2to about ∼2×10−6A/cm2using He dilution at 250°C, and the vacuum anneal of the nc-Si:H lowered it by an additional factor of two. Thus we observe that both the nc-Si:H anneal and the SiO2deposition at high He dilution lessen the gate leakage current.

Thermal-CVD Produced Amorphous-Silicon Thin-Film Transistors-Ambipolar Characteristics

1990 ◽  
Vol 192 ◽  
Author(s):  
Hiroshi Kanoh ◽  
Osamu Sugiura ◽  
Paul A. Breddels ◽  
Masakiyo Matsumura
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Electron Mobility ◽  
Thin Film Transistors ◽  
Field Effect ◽  
Hole Mobility ◽  
Silicon Thin Film ◽  
Free Hole ◽  
Thermal Cvd ◽  
Channel Mode

ABSTRACTAmorphous-silicon thin-film transistors (a-Si TFTs) have been fabricated by using an a-Si layer deposited by low-temperature thermal-CVD method using higher silanes. The TFT with thermally grown SiO2 gate was operated in both the n-channel mode and the p-channel mode. The maximum field-effect mobility and typical on/off current ratio were 1.5 cm2/Vs and 107 for the n-channel operation, and 0.2 cm2/Vs and 106 for the p-channel operation, respectively. Free electron mobility in the conduction band and free hole mobility in the valence band have been estimated, using the temperature dependence of the field-effect mobilities. It was found that the hole mobility is as high as the electron mobility.

Non-ohmic contact resistance and field-effect mobility in nanocrystalline silicon thin film transistors

2008 ◽  
Vol 93 (16) ◽  
pp. 163503 ◽  
Author(s):  
Arman Ahnood ◽  
Khashayar Ghaffarzadeh ◽  
Arokia Nathan ◽  
Peyman Servati ◽  
Flora Li ◽  
...  
Keyword(s):  
Thin Film ◽  
Contact Resistance ◽  
Ohmic Contact ◽  
Thin Film Transistors ◽  
Field Effect ◽  
Nanocrystalline Silicon ◽  
Field Effect Mobility ◽  
Silicon Thin Film
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