Effects of Metal Nanocrystals and Traps in Tunneling Rate Measurements in Metal Nanocrystal Based Carbon Nanotube Memory

2006 ◽  
Vol 963 ◽  
Author(s):  
Udayan Ganguly ◽  
Tuo-Hung Hou ◽  
Edwin Kan
Keyword(s):  
Carbon Nanotube ◽  
Electric Fields ◽  
Flash Memory ◽  
Low Voltage ◽  
Memory Device ◽  
Tunneling Rate ◽  
Direct Tunneling ◽  
High Electric Fields ◽  
Tunneling Behavior ◽  
Tunneling Rates

ABSTRACTThe metal nanocrystal (NC) based carbon nanotube (CNT) memory device has been probed with tunneling rate measurements. Firstly, tunneling behavior at two temperatures (300K and 10K) is reported here to demonstrate the distinct charge tunneling behavior for traps versus NCs and understand their relative contributions to program operations. Low temperature measurements show clear differentiation for two regimes of quantum transport. The FN tunneling regime exhibits strong bias dependence and dominates at high electric fields producing larger tunneling rates than the direct tunneling regime. In comparison to traps, the metal NCs repel potential contours and hence produce higher electric fields that enhance tunneling. The FN tunneling diminishes when the charging of the nanocrystal or traps decreases (relaxes) the electric field in the tunnel dielectric (TD) enough for the low field direct tunneling to dominate. The direct tunneling occurs at low fields, and is less sensitive to electric fields. The NCs demonstrate faster tunneling which can be ascribed to their large tunneling cross-section compared to traps. This is despite the relative proximity of traps to the channel in our structure. Secondly, the tunneling rates for two different TDs of similar EOT (under linear approximation) have been characterized and compared. They are a homogenous evaporated SiO2 and layered dielectric consisting of an evaporated SiO2 and ALD Al2O3 stack. While the evaporated SiO2 based TD demonstrates the distinct NC versus trap tunnel rate performance, the layered TD demonstrates stronger resistance to tunneling to the NCs. This result is consistent with the low tunneling rates demonstrated in Al2O3 elsewhere. Finally, the program performance of the NC-CNT memory device is evaluated as 0.5 V threshold voltage (VT) shift for a charging pulse of 9V and 100 μs. Combining with previous results, this indicates that NC-CNT memory is a promising candidate for low voltage, fast, multi-level cell (MLC) operation with sub-lithographic (self-assembled) features for sub 30 nm FLASH memory node. From the device physics perspective, these measurements may serve as the calibration and validation for advanced tunneling calculations and device modeling for promising nanoscale charge-based non-volatile memories.

Modified ITAT Model for Data Retention in Nanocrystals Based Flash Memory Gate Stack

2017 ◽  
Vol 45 ◽  
pp. 1-11
Author(s):  
Rasika Dhavse ◽  
Kumar Prashant ◽  
Chetan Dabhi ◽  
Anand Darji ◽  
R.M. Patrikar
Keyword(s):  
Flash Memory ◽  
Low Voltage ◽  
Flat Band ◽  
Data Retention ◽  
Gate Stack ◽  
Tunneling Model ◽  
Idle Mode ◽  
Direct Tunneling ◽  
Device Lifetime ◽  
P Type

This work applies combination of Direct Tunneling model and BSIM4 based ITAT model to explain the leakage of electrons from charged nanocrystals to p-type silicon substrate in data retention condition, for an ultra-thin tunnel oxide, low voltage programmable silicon nanocrystal based flash gate stack. Basic expressions of these models are modified to incorporate the nanocrystals related charge leakage in idle mode. The concept is supported by simulating these models and comparing them with the experimental data. Transition of electrons is considered as a result of Direct Tunneling and their trapping de-trapping via water related hydrogen traps. However, it is found that modified ITAT mechanism is the dominant one. Flat-band voltage shift profile fits accurately with the model with an extrapolated 10 years device lifetime without memory closure. 3 nm thick tunnel oxide and 100 nm sized nanocrystal fabrication with Electron Beam Lithography are main features of the devices.

CARBON NANOTUBE BASED NONVOLATILE MEMORY DEVICES

2006 ◽  
Vol 16 (04) ◽  
pp. 959-975 ◽  
Author(s):  
YUEGANG ZHANG
Keyword(s):  
Carbon Nanotube ◽  
Flash Memory ◽  
Nonvolatile Memory ◽  
Memory Performance ◽  
Memory Device ◽  
Floating Gate ◽  
Memory Devices ◽  
Memory Cells ◽  
Nonvolatile Memory Devices ◽  
Electrostatic Coupling

The technology progress and increasing high density demand have driven the nonvolatile memory devices into nanometer scale region. There is an urgent need of new materials to address the high programming voltage and current leakage problems in the current flash memory devices. As one of the most important nanomaterials with excellent mechanical and electronic properties, carbon nanotube has been explored for various nonvolatile memory applications. While earlier proposals of "bucky shuttle" memories and nanoelectromechanical memories remain as concepts due to fabrication difficulty, recent studies have experimentally demonstrated various prototypes of nonvolatile memory cells based on nanotube field-effect-transistor and discrete charge storage bits, which include nano-floating gate memory cells using metal nanocrystals, oxide-nitride-oxide memory stack, and more simpler trap-in-oxide memory devices. Despite of the very limited research results, distinct advantages of high charging efficiency at low operation voltage has been demonstrated. Single-electron charging effect has been observed in the nanotube memory device with quantum dot floating gates. The good memory performance even with primitive memory cells is attributed to the excellent electrostatic coupling of the unique one-dimensional nanotube channel with the floating gate and the control gate, which gives extraordinary charge sensibility and high current injection efficiency. Further improvement is expected on the retention time at room temperature and programming speed if the most advanced fabrication technology were used to make the nanotube based memory cells.

Low Voltage Operation of High-κ HfO2/TiO2/Al2O3Single Quantum Well for Nanoscale Flash Memory Device Applications

2008 ◽  
Vol 47 (3) ◽  
pp. 1818-1821 ◽  
Author(s):  
Siddheswar Maikap ◽  
Ting-Yu Wang ◽  
Pei-Jer Tzeng ◽  
Heng-Yuan Lee ◽  
Cha-Hsin Lin ◽  
...  
Keyword(s):  
Quantum Well ◽  
Flash Memory ◽  
Low Voltage ◽  
Memory Device ◽  
Low Voltage Operation ◽  
Device Applications

scholarly journals Large Area Silicon Carbide Vertical JFETs for 1200 V Cascode Switch Operation

2008 ◽  
Vol 2008 ◽  
pp. 1-8 ◽  
Author(s):  
Victor Veliadis ◽  
Ty McNutt ◽  
Megan Snook ◽  
Harold Hearne ◽  
Paul Potyraj ◽  
...  
Keyword(s):  
Electric Fields ◽  
Low Voltage ◽  
Voltage Drop ◽  
Short Circuit ◽  
Drain Voltage ◽  
Large Area ◽  
Active Device ◽  
Circuit Performance ◽  
Power Switches ◽  
High Electric Fields

SiC VJFETs are excellent candidates for reliable high-power/temperature switching as they only use pn junctions in the active device area where the high-electric fields occur. VJFETs do not suffer from forward voltage degradation, exhibit excellent short-circuit performance, and operate at 300°C. 0.19 cm2 1200 V normally-on and 0.15 cm2 low-voltage normally-off VJFETs were fabricated. The 1200-V VJFET outputs 53 A with a forward drain voltage drop of 2 V and a specific onstate resistance of 5.4 mΩ cm2. The low-voltage VJFET outputs 28 A with a forward drain voltage drop of 3.3 V and a specific onstate resistance of 15 mΩ cm2. The 1200-V SiC VJFET was connected in the cascode configuration with two Si MOSFETs and with a low-voltage SiC VJFET to form normally-off power switches. At a forward drain voltage drop of 2.2 V, the SiC/MOSFETs cascode switch outputs 33 A. The all-SiC cascode switch outputs 24 A at a voltage drop of 4.7 V.

Electron transfer from a carbon nanotube into vacuum under high electric fields

2009 ◽  
Vol 21 (19) ◽  
pp. 195302 ◽  
Author(s):  
L D Filip ◽  
R C Smith ◽  
J D Carey ◽  
S R P Silva
Keyword(s):  
Electron Transfer ◽  
Carbon Nanotube ◽  
Electric Fields ◽  
High Electric Fields

Nanocrystals in High-k Dielectric Stacks for Non-Volatile Memory Applications

2006 ◽  
Vol 51 ◽  
pp. 156-166 ◽  
Author(s):  
Marco Fanciulli ◽  
Michele Perego ◽  
Caroline Bonafos ◽  
A. Mouti ◽  
S. Schamm ◽  
...  
Keyword(s):  
Leakage Current ◽  
Retention Time ◽  
Flash Memory ◽  
Low Voltage ◽  
Memory Device ◽  
Research Strategies ◽  
High K ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
High K Materials

The possibility to use semiconducting or metallic nanocrystals (ncs) embedded in a SiO2 matrix as charge storage elements in novel non volatile memory devices has been widely explored in the last ten years. The replacement of the continuous polysilicon layer of a conventional flash memory device by a 2-dimensional nanoparticle array presents several advantages but the fundamental trade-off between programming and data retention characteristics has not been overcome yet. The main problem is the limited retention time basically due to charge loss by leakage current through the ultra-thin SiO2 tunnelling dielectric. A longer retention time can be achieved by increasing the tunnel oxide thickness. This however implies higher operating voltages and consequently a reduced write/erase speed. Using high-k materials for tunnel and/or gate oxide it is in principle possible to achieve the goal of a low voltage non volatile memory device. The high dielectric constant of these materials allows using thicker tunnel oxide reducing leakage current. Several approaches have been explored to synthesise ordered arrays of ncs in SiO2 but the transfer of these methodologies to the synthesis of 2-d array of ncs in high-k materials is not trivial. In this work we address the material science issues related to the synthesis of metallic and semiconducting ncs in high-k materials using different techniques. A detailed review of the state of the art in the field is presented and further research strategies are suggested.

Atomic Spectroscopy in the FIM

1986 ◽  
Vol 44 ◽  
pp. 758-761
Author(s):  
J. J. Hren ◽  
S. D. Walck
Keyword(s):  
Electron Microscope ◽  
Electric Fields ◽  
Atom Probe ◽  
Atomic Spectroscopy ◽  
Single Atom ◽  
Statistical Sampling ◽  
Commercial Instrument ◽  
Available Technology ◽  
High Electric Fields ◽  
Field Ion Microscope

The field ion microscope (FIM) has had the ability to routinely image the surface atoms of metals since Mueller perfected it in 1956. Since 1967, the TOF Atom Probe has had single atom sensitivity in conjunction with the FIM. “Why then hasn't the FIM enjoyed the success of the electron microscope?” The answer is closely related to the evolution of FIM/Atom Probe techniques and the available technology. This paper will review this evolution from Mueller's early discoveries, to the development of a viable commercial instrument. It will touch upon some important contributions of individuals and groups, but will not attempt to be all inclusive. Variations in instrumentation that define the class of problems for which the FIM/AP is uniquely suited and those for which it is not will be described. The influence of high electric fields inherent to the technique on the specimens studied will also be discussed. The specimen geometry as it relates to preparation, statistical sampling and compatibility with the TEM will be examined.

Carrier Profiling of the 10-nm-order Structure in a 3D Flash Memory Cell Using Scanning Nonlinear Dielectric Microscopy

2019 ◽  
Author(s):  
Jun Hirota ◽  
Ken Hoshino ◽  
Tsukasa Nakai ◽  
Kohei Yamasue ◽  
Yasuo Cho
Keyword(s):  
Spatial Resolution ◽  
Flash Memory ◽  
Analytical Techniques ◽  
Memory Cell ◽  
Memory Device ◽  
Floating Gate ◽  
Order Structure ◽  
Carrier Distribution ◽  
Nonlinear Dielectric ◽  
Flash Memory Cell

Abstract In this paper, the authors report their successful attempt to acquire the scanning nonlinear dielectric microscopy (SNDM) signals around the floating gate and channel structures of the 3D Flash memory device, utilizing the custom-built SNDM tool with a super-sharp diamond tip. The report includes details of the SNDM measurement and process involved in sample preparation. With the super-sharp diamond tips with radius of less than 5 nm to achieve the supreme spatial resolution, the authors successfully obtained the SNDM signals of floating gate in high contrast to the background in the selected areas. They deduced the minimum spatial resolution and seized a clear evidence that the diffusion length differences of the n-type impurity among the channels are less than 21 nm. Thus, they concluded that SNDM is one of the most powerful analytical techniques to evaluate the carrier distribution in the superfine three dimensionally structured memory devices.

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