Pre-applied Inter Chip Fill Material and Process for Advanced 3D Chip Stack

2009 ◽  
Vol 1195 ◽  
Author(s):  
Akihiro Horibe ◽  
Fumiaki Yamada
Keyword(s):  
High Temperature ◽  
Mechanical Stress ◽  
High Performance ◽  
Process Time ◽  
Narrow Gap ◽  
Device Structure ◽  
Temperature Cycles ◽  
Fine Pitch ◽  
3D Stacking ◽  
Joining Process

AbstractTo pursue further performance improvement of semiconductor devices, threedimensional (3D) chip integration with TSV would be one of the key technologies in the next decade. Inter Chip Fill (ICF) is a resin to fill gaps between chips, and it would be an important component for highly reliable and durable 3D integrated devices. High performance 3D devices require fine pitch interconnections with small bumps for high pin count with high bandwidth. Smaller bumps lead to narrow gap design between stacked chips inevitably, and the narrow gap is expected to reduce heat resistance and thermo-mechanical stress. However it makes resin filling and flux cleaning processes harder. A preapplied ICF process is one of the potential methods to fill the narrow gaps with a resin. The material is halfcured resin applied on a wafer by spin-coating or film-lamination before chip integration. Flux cleaning process can be eliminated by adding fluxing function in the resin components. Major concerns of multiple chip 3D stacking process are repeated high temperature cycles of metal-joining, and long process time as a result. We are proposing “Stack Joining process” that enables 3D multi chip joining at one time instead of sequential chip by chip joining. In this process, multiple chips are aligned and temporarily stacked sequentially using adhesivity which the ICF has between Tg and initiation temperature of polymerization, and finally all metal bumps of stacked chips are melted and joined altogether. This process can substantially reduces repeated high temperature cycles and process time. As a result this technique could mitigate degradation of device materials.We successfully stacked chips by using the pre-applied ICF which was designed for advanced 3D chip stack having full area array and narrow gap (less than 10um) connections. In this paper, we explain the Stack Joining process flow and conditions. We also discuss the cause of mechanical stress within the stacked chip and required material features of the pre-applied ICF and device structure to reduce the stress.

High Thermal Conductive Inter Chip Fill for 3D-IC through Pre-applied Joining Process

2013 ◽  
Vol 2013 (1) ◽  
pp. 000408-000413
Author(s):  
Y. Kawase ◽  
M. Ikemoto ◽  
M. Yamazaki ◽  
M. Sugiyama ◽  
H. Kiritani ◽  
...  
Keyword(s):  
High Performance ◽  
Three Dimensional ◽  
Narrow Gap ◽  
Flux Agent ◽  
3D Ic ◽  
Conductive Materials ◽  
Highly Active ◽  
Fine Pitch ◽  
Joining Process ◽  
Active Flux

Three dimensional (3D) IC has been proposed for high performance and low power in recent years. Due to the narrow gap between stacked chips and fine pitch of bumps, new inter chip fill (ICF) which can be used for pre-applied ICF process is required. The heat generation of 3D-IC is higher than 2D, so that a high thermal conductive inter chip fill (HT-ICF) is simultaneously required to dissipate the heat from 3D-IC and for the purpose of pre-applied ICF and HT-ICF, highly active flux agent and thermal conductive materials such as filler and matrix have been called for at the same time. In this study, some kind of materials were prepared, synthesized and optimized for the HT-ICF, and we evaluated its characteristic and confirmed applicability to pre-applied joining for 3D-IC.

No Flow Underfill Process Development for Fine Pitch Flip Chip Silicon to Silicon Wafer Level Integration

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000708-000735 ◽  
Author(s):  
Zhaozhi Li ◽  
John L. Evans ◽  
Paul N. Houston ◽  
Brian J. Lewis ◽  
Daniel F. Baldwin ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Process Development ◽  
Low Cost ◽  
Three Dimensional ◽  
High Yield ◽  
Process Time ◽  
Assembly Process ◽  
Wafer Level ◽  
Fine Pitch

The industry has witnessed the adoption of flip chip for its low cost, small form factor, high performance and great I/O flexibility. As the Three Dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon to silicon assembly, is gaining more and more popularity. Most flip chip packages require underfill to overcome the CTE mismatch between the die and substrate. Although the flip chip to wafer assembly is a silicon to silicon integration, the underfill is necessary to overcome the Z-axis thermal expansion as well as the mechanical impact stresses that occur during shipping and handling. No flow underfill is of special interest for the wafer level flip chip assembly as it can dramatically reduce the process time as well as bring down the average package cost since there is a reduction in the number of process steps and the dispenser and cure oven that would be necessary for the standard capillary underfill process. Chip floating and underfill outgassing are the most problematic issues that are associated with no flow underfill applications. The chip floating is normally associated with the size/thickness of the die and volume of the underfill dispensed. The outgassing of the no flow underfill is often induced by the reflow profile used to form the solder joint. In this paper, both issues will be addressed. A very thin, fine pitch flip chip and 2x2 Wafer Level CSP tiles are used to mimic the assembly process at the wafer level. A chip floating model will be developed in this application to understand the chip floating mechanism and define the optimal no flow underfill volume needed for the process. Different reflow profiles will be studied to reduce the underfill voiding as well as improve the processing yield. The no flow assembly process developed in this paper will help the industry understand better the chip floating and voiding issues regarding the no flow underfill applications. A stable, high yield, fine pitch flip chip no flow underfill assembly process that will be developed will be a very promising wafer level assembly technique in terms of reducing the assembly cost and improving the throughput.

Pre-Applied Underfill (PAUF) for Fine Pitch Flip Chip 3D Chip Stacking

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001432-001451
Author(s):  
Anupam Choubey ◽  
E. Anzures ◽  
A. Dhoble ◽  
D. Fleming ◽  
M. Gallagher ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Fatigue Testing ◽  
Electrical Performance ◽  
Process Time ◽  
Wafer Level ◽  
Fine Pitch ◽  
Semiconductor Packages ◽  
Reliability Performance ◽  
3D Chip Stacking

Current demands of the industry on performance and cost has triggered the electronics industry to use high I/O counts semiconductor packages. Copper pillar technology has been widely adopted for introducing high I/O counts in Flip Chip and 3D Chip Stacking. With the introduction of flipchip technology new avenues have been generated involving 3D chip stacking to expand the need for high performance. With the increase in the demand for high density, copper pillar technology is being adopted in the industry to address the fine pitch requirements in addition to providing enhanced thermal and electrical performance. For this study, Copper pillars and SnAg were electrolytically deposited using Dow's electroplating chemistry on internally developed test structures. After plating, wafers were diced and bonded using thermocompression bonding techniques. Copper pillar technology has been enabled to pass reliability requirements by using Underfill materials during the bonding. Underfill materials assist in redistributing the stress generated during reliability such as thermal fatigue testing. Out of the several Underfill technologies available, we have focused on pre-applied or wafer level underfill materials with 60% silica filler for this study. In the pre-applied underfill process the underfill is applied prior to bonding by coating directly on the whole wafer. Pre-applied underfill reduces the underfill dispense process time by being present prior to bonding. In this study, we have demonstrated the application of wafer level underfill for fine pitch bonding of internally developed test vehicles with SnAg-capped copper pillars with 25 μm diameter and 50 μm bump pitch. This paper demonstrates bonding alignment for fine pitch assembly with wafer level underfill to achieve 100% good solder joins after bonding. Wafer level underfill has been demonstrated successfully to bond and pass JEDEC level 3 preconditioning and standard TCT, HTS and HAST reliability tests. This paper also discusses defect mechanisms which have been found to optimize the bonding process and reliability performance. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-6-12.

Assembly Process Development for Fine Pitch Flip Chip Silicon-to-Silicon 3D Wafer Level Integration with No Flow Underfill

2010 ◽  
Vol 7 (3) ◽  
pp. 146-151 ◽  
Author(s):  
Zhaozhi Li ◽  
Sangil Lee ◽  
Brian J. Lewis ◽  
Paul N. Houston ◽  
Daniel F. Baldwin ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Process Development ◽  
Low Cost ◽  
Three Dimensional ◽  
Process Time ◽  
Wafer Level ◽  
Fine Pitch ◽  
3D Packaging ◽  
Small Form Factor

The industry has witnessed the adoption of the flip chip for its low cost, small form factor, high performance, and great I/O flexibility. As three-dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon-to-silicon assembly, is gaining more and more popularity. No flow underfill is of special interest for the wafer level flip chip assembly, as it can dramatically reduce the process time and the cost per package, due to the reduction in the number of process steps as well as the dispenser and cure oven that would otherwise be necessary for the standard capillary underfill process. This paper introduces the development of a no flow underfill process for a sub-100 micron pitch flip chip to CSP wafer level assembly. Challenges addressed include the no flow underfill reflow profile study, underfill dispense amount study, chip floating control, underfill voiding reduction, and yield improvement. Also, different no flow underfill candidates were investigated to determine the best performing processing material.

Non-destructive In-line IMC Thickness Measurement Using Acoustic Metrology for 3D Stacking

2019 ◽  
Vol 2019 (1) ◽  
pp. 000274-000279
Author(s):  
M. Mehendale ◽  
L. Hou ◽  
R. Mair ◽  
M. Kotelyanskii ◽  
M. Liebens ◽  
...  
Keyword(s):  
High Performance ◽  
Spot Size ◽  
Thickness Measurement ◽  
Fine Pitch ◽  
Thermocompression Bonding ◽  
Vertical Interconnects ◽  
3D Stacking ◽  
Silicon Vias ◽  
Accuracy And Repeatability ◽  
Non Destructive

Abstract The constant demand for small-feature-size, high performance and dense I/O applications have necessitated the development of fine-pitch vertical interconnects for 3-D integration. Microbumps and through silicon vias enable the high-density vertical interconnects. As microbumps scale, intermetallic compound formation during thermocompression bonding and its impact on reliability is a concern. In this paper, we describe the application of picosecond acoustic metrology technology as a viable option for non-destructive characterization of the intermetallic compounds. The small spot size technology allows measurement on small bumps, with very good accuracy and repeatability.

ARMCO PH 13-8Mo

Alloy Digest ◽  
1990 ◽  
Vol 39 (2) ◽  
Keyword(s):  
Fracture Toughness ◽  
Corrosion Resistance ◽  
High Temperature ◽  
Physical Properties ◽  
Stress Corrosion ◽  
Tensile Properties ◽  
High Performance ◽  
High Strength ◽  
Heat Treating ◽  
Temperature Performance

Abstract ARMCO PH 13-8Mo is designed for high-performance applications requiring high strength coupled with excellent resistance to corrosion and stress corrosion. It has excellent toughness, good transverse properties and excellent forgeability. This datasheet provides information on composition, physical properties, hardness, elasticity, and tensile properties as well as fracture toughness. It also includes information on low and high temperature performance, and corrosion resistance as well as forming, heat treating, machining, and joining. Filing Code: SS-224. Producer or source: Baltimore Specialty Steels Corporation. Originally published May 1969, revised February 1990.

INCOLOY ALLOY 864

Alloy Digest ◽  
1998 ◽  
Vol 47 (2) ◽  
Keyword(s):  
Corrosion Resistance ◽  
High Temperature ◽  
Mechanical Strength ◽  
High Performance ◽  
Exhaust System ◽  
Good Combination ◽  
Fatigue Properties ◽  
Temperature Performance ◽  
Incoloy Alloy ◽  
Oxidation And Corrosion

Abstract Incoloy Alloy 864 is a high performance alloy developed specifically for automotive exhaust system flexible couplings and other exhaust applications. The alloy has a good combination of oxidation and corrosion resistance, with good mechanical strength, stability, and fatigue properties. This datasheet provides information on composition, physical properties, and elasticity. It also includes information on high temperature performance and corrosion resistance as well as joining. Filing Code: SS-708. Producer or source: Inco Alloys International Inc.

HITACHI METALS SLD-MAGIC

Alloy Digest ◽  
2020 ◽  
Vol 69 (10) ◽  
Keyword(s):  
High Temperature ◽  
Physical Properties ◽  
Tool Steel ◽  
High Performance ◽  
Cold Work ◽  
Heat Treating ◽  
Temperature Performance ◽  
Mold Fabrication ◽  
Cold Work Tool Steel

Abstract Hitachi Metals SLD-Magic is a high-performance alloy cold-work tool steel that is characterized by improved mold lifespan and easy mold fabrication. This datasheet provides information on composition, physical properties, hardness, elasticity as well as fatigue. It also includes information on low and high temperature performance as well as heat treating, machining, and joining. Filing Code: TS-802. Producer or source: Hitachi Metals Ltd.

Use of activated carbon to remove undesirable residual amylase from refinery streams

2017 ◽  
pp. 96-103 ◽  
Author(s):  
Gillian Eggleston ◽  
Isabel Lima ◽  
Emmanuel Sarir ◽  
Jack Thompson ◽  
John Zatlokovicz ◽  
...  
Keyword(s):  
Activated Carbon ◽  
High Temperature ◽  
High Performance ◽  
Activated Carbons ◽  
Amylase Activity ◽  
Sugar Industry ◽  
End User ◽  
Customer Complaints ◽  
Carry Over ◽  
Very High

In recent years, there has been increased world-wide concern over residual (carry-over) activity of mostly high temperature (HT) and very high temperature (VHT) stable amylases in white, refined sugars from refineries to various food and end-user industries. HT and VHT stable amylases were developed for much larger markets than the sugar industry with harsher processing conditions. There is an urgent need in the sugar industry to be able to remove or inactivate residual, active amylases either in factory or refinery streams or both. A survey of refineries that used amylase and had activated carbon systems for decolorizing, revealed they did not have any customer complaints for residual amylase. The use of high performance activated carbons to remove residual amylase activity was investigated using a Phadebas® method created for the sugar industry to measure residual amylase in syrups. Ability to remove residual amylase protein was dependent on the surface area of the powdered activated carbons as well as mixing (retention) time. The activated carbon also had the additional benefit of removing color and insoluble starch.

Mechanism-Based Design for High-Temperature, High-Performance Composites. Book 1

1997 ◽  
Author(s):  
Anthony G. Evans ◽  
Frederick A. Leckie ◽  
J. W. Hutchinson
Keyword(s):  
High Temperature ◽  
High Performance
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