High Thermal Conductive Inter Chip Fill for 3D-IC through Pre-applied Joining Process

2013 ◽  
Vol 2013 (1) ◽  
pp. 000408-000413
Author(s):  
Y. Kawase ◽  
M. Ikemoto ◽  
M. Yamazaki ◽  
M. Sugiyama ◽  
H. Kiritani ◽  
...  
Keyword(s):  
High Performance ◽  
Three Dimensional ◽  
Narrow Gap ◽  
Flux Agent ◽  
3D Ic ◽  
Conductive Materials ◽  
Highly Active ◽  
Fine Pitch ◽  
Joining Process ◽  
Active Flux

Three dimensional (3D) IC has been proposed for high performance and low power in recent years. Due to the narrow gap between stacked chips and fine pitch of bumps, new inter chip fill (ICF) which can be used for pre-applied ICF process is required. The heat generation of 3D-IC is higher than 2D, so that a high thermal conductive inter chip fill (HT-ICF) is simultaneously required to dissipate the heat from 3D-IC and for the purpose of pre-applied ICF and HT-ICF, highly active flux agent and thermal conductive materials such as filler and matrix have been called for at the same time. In this study, some kind of materials were prepared, synthesized and optimized for the HT-ICF, and we evaluated its characteristic and confirmed applicability to pre-applied joining for 3D-IC.

Pre-Applied Inter Chip Fill for 3D-IC Chip Joining

2015 ◽  
Author(s):  
Yasuhiro Kawase ◽  
Makoto Ikemoto ◽  
Masaya Sugiyama ◽  
Hidehiro Yamamoto ◽  
Hideki Kiritani
Keyword(s):  
Thermal Conductivity ◽  
Integrated Circuits ◽  
High Performance ◽  
Three Dimensional ◽  
Conductive Filler ◽  
3D Ic ◽  
Fine Pitch ◽  
Silica Filler ◽  
Conductive Fillers ◽  
Process Compatibility

Three dimensional integrated circuits (3D-IC) have been proposed for the purpose of low power and high performance in recent years. Pre-applied inter chip fill is required for fine pitch interconnections, large chips, and also thin chips. In addition to them, pre-applied joining process with high thermal conductive inter chip fill (HT-ICF) is strongly required for the cooling of 3D-IC. Some kinds of matrix resins and thermal conductive fillers were simulated and evaluated for pre-applied ICF. As a result, matrix and cure agent appeared to be important to both pre-applied ICF process compatibility and thermal conductivity, so that we’d selected epoxy type matrix based on controlling super molecular structure due to its mesogen unit. And not only matrix but also filler appeared to be the key to improve thermal conductivity for pre-applied ICF at the same time. The thermal conductivity of conventional silica filler was only 1W/mK, so that, taking into account of thermal conductivity, density and its stability, we’d selected aluminum oxide and boron nitride as thermal conductive filler and optimized HT-ICF for pre-applied process. After composite was mixed and cured, some physical properties were measured and thermal conductivity was 1.8W/mK, CTE was below 21ppm/K and Tg was 120°C. Furthermore, new high thermal conductive filler was also studied. We’d synthesized completely new spherical BN (diameter <5um) and applied it to HT-ICF and the thermal conductivity was almost two times higher than conventional BN. In this study, we confirmed ICF physical characteristics and its pre-applied joining for 3D-IC and void-less joining was also discussed.

Pre-applied Inter Chip Fill Material and Process for Advanced 3D Chip Stack

2009 ◽  
Vol 1195 ◽  
Author(s):  
Akihiro Horibe ◽  
Fumiaki Yamada
Keyword(s):  
High Temperature ◽  
Mechanical Stress ◽  
High Performance ◽  
Process Time ◽  
Narrow Gap ◽  
Device Structure ◽  
Temperature Cycles ◽  
Fine Pitch ◽  
3D Stacking ◽  
Joining Process

AbstractTo pursue further performance improvement of semiconductor devices, threedimensional (3D) chip integration with TSV would be one of the key technologies in the next decade. Inter Chip Fill (ICF) is a resin to fill gaps between chips, and it would be an important component for highly reliable and durable 3D integrated devices. High performance 3D devices require fine pitch interconnections with small bumps for high pin count with high bandwidth. Smaller bumps lead to narrow gap design between stacked chips inevitably, and the narrow gap is expected to reduce heat resistance and thermo-mechanical stress. However it makes resin filling and flux cleaning processes harder. A preapplied ICF process is one of the potential methods to fill the narrow gaps with a resin. The material is halfcured resin applied on a wafer by spin-coating or film-lamination before chip integration. Flux cleaning process can be eliminated by adding fluxing function in the resin components. Major concerns of multiple chip 3D stacking process are repeated high temperature cycles of metal-joining, and long process time as a result. We are proposing “Stack Joining process” that enables 3D multi chip joining at one time instead of sequential chip by chip joining. In this process, multiple chips are aligned and temporarily stacked sequentially using adhesivity which the ICF has between Tg and initiation temperature of polymerization, and finally all metal bumps of stacked chips are melted and joined altogether. This process can substantially reduces repeated high temperature cycles and process time. As a result this technique could mitigate degradation of device materials.We successfully stacked chips by using the pre-applied ICF which was designed for advanced 3D chip stack having full area array and narrow gap (less than 10um) connections. In this paper, we explain the Stack Joining process flow and conditions. We also discuss the cause of mechanical stress within the stacked chip and required material features of the pre-applied ICF and device structure to reduce the stress.

CMP Compatibility of Partially Cured Benzocyclobutene (BCB) for a Via-First 3D IC Process

2005 ◽  
Vol 867 ◽  
Author(s):  
J. J. McMahon ◽  
F. Niklaus ◽  
R. J. Kumar ◽  
J. Yu ◽  
J.Q. Lu ◽  
...  
Keyword(s):  
High Performance ◽  
Removal Rate ◽  
Three Dimensional ◽  
Surface Damage ◽  
Wafer Level ◽  
Razor Blade ◽  
3D Ic ◽  
3D Technology ◽  
Process Step ◽  
Wide Range

AbstractWafer-level three dimensional (3D) IC technology offers the promise of decreasing RC delays by reducing long interconnect lines in high performance ICs. This paper focuses on a viafirst 3D IC platform, which utilizes a back-end-of-line (BEOL) compatible damascene-patterned layer of copper and Benzocyclobutene (BCB). This damascene-patterned copper/BCB serves as a redistribution layer between two fully fabricated wafer sets of ICs and offers the potential of high bonding strength and low contact resistance for inter-wafer interconnects between the wafer pair. The process would thus combine the electrical advantages of 3D technology using Cu-to-Cu bonding with the mechanical advantages of 3D technology using BCB-to-BCB bonding.In this work, partially cured BCB has been evaluated for copper damascene patterning using commercially available CMP slurries as a key process step for a via-first 3D process flow. BCB is spin-cast on 200 mm wafers and cured at temperatures ranging from 190°C to 250°C, providing a wide range of crosslink percentage. These films are evaluated for CMP removal rate, surface damage (surface scratching and embedded abrasives), and planarity with commercially available copper CMP slurries. Under baseline process parameters, erosion, and roughness changes are presented for single-level damascene test patterns. After wafers are bonded under controlled temperature and pressure, the bonding interface is inspected optically using glass-to-silicon bonded wafers, and the bond strength is evaluated by a razor blade test.

scholarly journals Evaluation of the Potential Electromagnetic Interference in Vertically Stacked 3D Integrated Circuits

2020 ◽  
Vol 10 (3) ◽  
pp. 748
Author(s):  
Dipesh Kapoor ◽  
Cher Ming Tan ◽  
Vivek Sangwan
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Electromagnetic Interference ◽  
High Speed ◽  
High Performance ◽  
Near Field ◽  
Three Dimensional ◽  
3D Ic ◽  
Three Dimensional Integrated Circuit ◽  
The Impact

Advancements in the functionalities and operating frequencies of integrated circuits (IC) have led to the necessity of measuring their electromagnetic Interference (EMI). Three-dimensional integrated circuit (3D-IC) represents the current advancements for multi-functionalities, high speed, high performance, and low-power IC technology. While the thermal challenges of 3D-IC have been studied extensively, the influence of EMI among the stacked dies has not been investigated. With the decreasing spacing between the stacked dies, this EMI can become more severe. This work demonstrates the potential of EMI within a 3D-IC numerically, and determines the minimum distance between stack dies to reduce the impact of EMI from one another before they are fabricated. The limitations of using near field measurement for the EMI study in stacked dies 3D-IC are also illustrated.

Nanoporous Metals for Catalytic and Optical Applications

MRS Bulletin ◽  
2009 ◽  
Vol 34 (8) ◽  
pp. 569-576 ◽  
Author(s):  
Yi Ding ◽  
Mingwei Chen
Keyword(s):  
Optical Properties ◽  
Fuel Cell ◽  
High Performance ◽  
Electrode Materials ◽  
Three Dimensional ◽  
Functional Materials ◽  
Porous Network ◽  
Highly Active ◽  
Wide Range ◽  
Nanoporous Metals

AbstractNanoporous metals (NPMs) made by dealloying represent a class of functional materials with the unique structural properties of mechanical rigidity, electrical conductivity, and high corrosion resistance. They also possess a porous network structure with feature dimensions tunable within a wide range from a few nanometers to several microns. Coupled with a rich surface chemistry for further functionalization, NPMs have great potential for applications in heterogeneous catalysis, electrocatalysis, fuel cell technologies, biomolecular sensing, surface-enhanced Raman scattering (SERS), and plasmonics. This article summarizes recent advances in some of these areas and, in particular, we focus on the discussion of microstructure, catalytic, and optical properties of nanoporous gold (NPG). With advanced electron microscopy, three-dimensional tomographic reconstructions of NPG have been realized that yield quantitative characterizations of key morphological parameters involved in the intricate structure. Catalytic and electrocatalytic investigations demonstrate that bare NPG is already catalytically active for many important reactions such as CO and glucose oxidation. Surface functionalization with other metals, such as Pt, produces very efficient electrocatalysts, which have been used as promising fuel cell electrode materials with very low precious metal loading. Additionally, NPG and related materials possess outstanding optical properties in plasmonics and SERS. They hold promise to act as highly active, stable, and economically affordable substrates in high-performance instrumentation applications for chemical inspection and biomolecular diagnostics. Finally, we conclude with some perspectives that appear to warrant future investigation.

No Flow Underfill Process Development for Fine Pitch Flip Chip Silicon to Silicon Wafer Level Integration

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000708-000735 ◽  
Author(s):  
Zhaozhi Li ◽  
John L. Evans ◽  
Paul N. Houston ◽  
Brian J. Lewis ◽  
Daniel F. Baldwin ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Process Development ◽  
Low Cost ◽  
Three Dimensional ◽  
High Yield ◽  
Process Time ◽  
Assembly Process ◽  
Wafer Level ◽  
Fine Pitch

The industry has witnessed the adoption of flip chip for its low cost, small form factor, high performance and great I/O flexibility. As the Three Dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon to silicon assembly, is gaining more and more popularity. Most flip chip packages require underfill to overcome the CTE mismatch between the die and substrate. Although the flip chip to wafer assembly is a silicon to silicon integration, the underfill is necessary to overcome the Z-axis thermal expansion as well as the mechanical impact stresses that occur during shipping and handling. No flow underfill is of special interest for the wafer level flip chip assembly as it can dramatically reduce the process time as well as bring down the average package cost since there is a reduction in the number of process steps and the dispenser and cure oven that would be necessary for the standard capillary underfill process. Chip floating and underfill outgassing are the most problematic issues that are associated with no flow underfill applications. The chip floating is normally associated with the size/thickness of the die and volume of the underfill dispensed. The outgassing of the no flow underfill is often induced by the reflow profile used to form the solder joint. In this paper, both issues will be addressed. A very thin, fine pitch flip chip and 2x2 Wafer Level CSP tiles are used to mimic the assembly process at the wafer level. A chip floating model will be developed in this application to understand the chip floating mechanism and define the optimal no flow underfill volume needed for the process. Different reflow profiles will be studied to reduce the underfill voiding as well as improve the processing yield. The no flow assembly process developed in this paper will help the industry understand better the chip floating and voiding issues regarding the no flow underfill applications. A stable, high yield, fine pitch flip chip no flow underfill assembly process that will be developed will be a very promising wafer level assembly technique in terms of reducing the assembly cost and improving the throughput.

Assembly Process Development for Fine Pitch Flip Chip Silicon-to-Silicon 3D Wafer Level Integration with No Flow Underfill

2010 ◽  
Vol 7 (3) ◽  
pp. 146-151 ◽  
Author(s):  
Zhaozhi Li ◽  
Sangil Lee ◽  
Brian J. Lewis ◽  
Paul N. Houston ◽  
Daniel F. Baldwin ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Process Development ◽  
Low Cost ◽  
Three Dimensional ◽  
Process Time ◽  
Wafer Level ◽  
Fine Pitch ◽  
3D Packaging ◽  
Small Form Factor

The industry has witnessed the adoption of the flip chip for its low cost, small form factor, high performance, and great I/O flexibility. As three-dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon-to-silicon assembly, is gaining more and more popularity. No flow underfill is of special interest for the wafer level flip chip assembly, as it can dramatically reduce the process time and the cost per package, due to the reduction in the number of process steps as well as the dispenser and cure oven that would otherwise be necessary for the standard capillary underfill process. This paper introduces the development of a no flow underfill process for a sub-100 micron pitch flip chip to CSP wafer level assembly. Challenges addressed include the no flow underfill reflow profile study, underfill dispense amount study, chip floating control, underfill voiding reduction, and yield improvement. Also, different no flow underfill candidates were investigated to determine the best performing processing material.

Pre-applied Inter Chip Fill for 3D-IC Joining

2014 ◽  
Vol 2014 (1) ◽  
pp. 000242-000246 ◽  
Author(s):  
Y. Kawase ◽  
M. Ikemoto ◽  
M. Sugiyama ◽  
H. Kiritani ◽  
F. Mizutani ◽  
...  
Keyword(s):  
Thermal Conductivity ◽  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Three Dimensional ◽  
Physical Characteristics ◽  
Two Dimensional ◽  
3D Ic ◽  
Thermal Compression ◽  
Low Viscosity

For the conventional two dimensional (2D) packaging of integrated circuit (IC), reflow and capillary under fill have been used for more than a decade. But for the purpose of low power and high performance of IC, three dimensional IC (3D-IC) have been proposed in recent years. In case of 3D-IC, both bump pitches and gaps between stacked thin chips should be fine and narrow, so that pre-applied inter chip fill (ICF) which is applied in thermal compression bonding have been proposed. In this process, not only low viscosity but also thermal conductivity is simultaneously required. In this study, some of selected epoxy based matrix and filler were simulated and evaluated for pre-applied ICF, we confirmed its process applicability to pre-applied chip bonding. Physical characteristics of cured ICF and void-less joining were also discussed.

scholarly journals Three-dimensional open nano-netcage electrocatalysts for efficient pH-universal overall water splitting

2019 ◽  
Vol 10 (1) ◽  
Author(s):  
Zewen Zhuang ◽  
Yu Wang ◽  
Cong-Qiao Xu ◽  
Shoujie Liu ◽  
Chen Chen ◽  
...  
Keyword(s):  
Active Sites ◽  
High Performance ◽  
High Efficiency ◽  
Sea Water ◽  
Three Dimensional ◽  
Water Electrolysis ◽  
High Exposure ◽  
Electrochemical Testing ◽  
Highly Active ◽  
Universal Applicability

Abstract High-efficiency water electrolysis is the key to sustainable energy. Here we report a highly active and durable RuIrOx (x ≥ 0) nano-netcage catalyst formed during electrochemical testing by in-situ etching to remove amphoteric ZnO from RuIrZnOx hollow nanobox. The dispersing-etching-holing strategy endowed the porous nano-netcage with a high exposure of active sites as well as a three-dimensional accessibility for substrate molecules, thereby drastically boosting the electrochemical surface area (ECSA). The nano-netcage catalyst achieved not only ultralow overpotentials at 10 mA cm−2 for hydrogen evolution reaction (HER; 12 mV, pH = 0; 13 mV, pH = 14), but also high-performance overall water electrolysis over a broad pH range (0 ~ 14), with a potential of mere 1.45 V (pH = 0) or 1.47 V (pH = 14) at 10 mA cm−2. With this universal applicability of our electrocatalyst, a variety of readily available electrolytes (even including waste water and sea water) could potentially be directly used for hydrogen production.

TSV Interposers With Embedded Microchannels for 3D IC and LED Integration

2011 ◽  
Author(s):  
John Lau ◽  
Heng-Chieh Chien ◽  
Ray Tain
Keyword(s):  
Structural Design ◽  
High Performance ◽  
Low Cost ◽  
Optical Devices ◽  
3D Ic ◽  
Moore’S Law ◽  
Moore's Law ◽  
Fine Pitch ◽  
Silicon Vias ◽  
Cooling Ability

A low-cost (with bare chips), high cooling ability and very low pressure drop 3D IC integration system-in-package (SiP) is designed and described. This system consists of a silicon interposer with through-silicon vias (TSV) and embedded fluidic microchannels, which carries all the Moore’s law chips and optical devices on its top and bottom surfaces. TSVs in the Moore’s law chips are optional but should be avoided. This novel structural design offers potential solutions for high-power, high-performance, high pin-count, ultra fine-pitch, small real-estate, and low-cost 3D IC SiP applications.

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