Charge Trapping Sites in nc-RuO Embedded ZrHfO High-k Nonvolatile Memories

2010 ◽  
Vol 1250 ◽  
Author(s):  
Chen-Han Lin ◽  
Yue Kuo
Keyword(s):  
Dielectric Film ◽  
Electrical Characterization ◽  
Charge Trapping ◽  
Mos Capacitor ◽  
Hole Trapping ◽  
Nonvolatile Memories ◽  
High K ◽  
Voltage Stress ◽  
Retention Characteristics ◽  
Trapping Sites

AbstractMaterials and electrical properties of the MOS capacitor containing nc-RuO embedded in the high-k ZrHfO dielectric film have been studied. The electron- and hole-trapping capacities and trapping sites in this kind of device were investigated using the constant voltage stress method, the frequency-dependent C-V measurement, and the retention characteristics. The negligible charge trapping phenomenon in the non-embedded device rules out the possibility of any trapping site in the bulk ZrHfO film or at the Si/ZrHfO interface. The electrical characterization result suggests that electrons are trapped in the bulk nc-RuO. However, holes have two possible trapping sites, i.e., in the bulk nc-RuO or at the nc-RuO/ZrHfO interface.

Impact of NO Annealing on Flatband Voltage Instability due to Charge Trapping in SiС MOS Devices

2016 ◽  
Vol 858 ◽  
pp. 599-602 ◽  
Author(s):  
Yoshihito Katsu ◽  
Takuji Hosoi ◽  
Yuichiro Nanen ◽  
Tsunenobu Kimoto ◽  
Takayoshi Shimura ◽  
...  
Keyword(s):  
High Stress ◽  
Charge Trapping ◽  
Oxide Semiconductor ◽  
Mos Capacitor ◽  
Hole Trapping ◽  
Uv Illumination ◽  
Mos Devices ◽  
Voltage Stress ◽  
Flatband Voltage

We evaluated the effect of NO annealing on hole trapping characteristic of SiC metal-oxide-semiconductor (MOS) capacitor by measuring flatband voltage (VFB) shifts during a constant negative gate voltage stress under UV illumination. Under low stress voltages, the VFB shift due to hole trapping was found to be suppressed by NO annealing. However, the VFB shift of the NO-annealed device increases significantly with stress time under high stress voltage conditions, while the device without NO annealing showed only a slight shift. This result implies that NO annealing enhances generation of hole traps, leading to the degradation of SiC-MOS devices in long-term reliability.

Behavior of Local Charge-Trapping Sites in La2O3–Al2O3Composite Films under Constant Voltage Stress

2007 ◽  
Vol 46 (4B) ◽  
pp. 1879-1884 ◽  
Author(s):  
Toshifumi Sago ◽  
Akiyoshi Seko ◽  
Mitsuo Sakashita ◽  
Akira Sakai ◽  
Masaki Ogawa ◽  
...  
Keyword(s):  
Charge Trapping ◽  
Constant Voltage ◽  
Local Charge ◽  
Voltage Stress ◽  
Trapping Sites

Electrical Characterization of High-k Dielectrics by Means of Flat-Band Voltage Transient Recording

2007 ◽  
Vol 996 ◽  
Author(s):  
Salvador Duenas ◽  
Helena Castán ◽  
Héctor García ◽  
Luis Bailón ◽  
Kaupo Kukli ◽  
...  
Keyword(s):  
Electric Fields ◽  
Electrical Characterization ◽  
Charge Trapping ◽  
Atomic Layer ◽  
Localized States ◽  
Oxide Semiconductor ◽  
Flat Band ◽  
Flat Band Voltage ◽  
High K ◽  
Mos Structures

AbstractWe have carried out a comparison between flat-band transients displayed in metal-oxide-semiconductor (MOS) structures fabricated on several atomic layer deposited (ALD) high-k dielectric films: HfO2, ZrO2, Al2O3, Ta2O5, TiO2, and Gd2O3. The gate voltage as a function of time is recorded while keeping constant the capacitance at the initial flat band condition (CFB). Since samples are in darkness, under no electric fields and no charge-injection conditions, transients must be due to charge trapping of localized states produced by electrons (holes) coming from the semiconductor by tunnelling. The process is assisted by phonons and it is therefore thermally activated. The temperature-transient amplitude relation follows an Arrhenius plot which provides the thermal activation energy of soft-optical phonons. Finally, we describe the dependencies of the flat-band voltage on the setup bias history (accumulation or inversion) and the hysteresis sign (clockwise or counter-clockwise) of the capacitance-voltage (C-V) characteristics of MOS structures.

Charge Trapping Memory Cell of TANOS (Oxide-SiN-Al2O3-TaN) Structure Erased by Fowler-Nordheim Tunneling of Holes

2006 ◽  
Vol 933 ◽  
Author(s):  
Chang-Hyun Lee ◽  
Changseok Kang ◽  
Yoocheol Shin ◽  
Jaesung Sim ◽  
Jongsun Sel ◽  
...  
Keyword(s):  
Energy Level ◽  
Threshold Voltage ◽  
Charge Trapping ◽  
Memory Cell ◽  
Floating Gate ◽  
Hole Trap ◽  
Hole Trapping ◽  
High K ◽  
Charge Trapping Memory ◽  
Nordheim Tunneling

ABSTRACTWe present the TANOS (Si-Oxide-SiN-Al2O3-TaN) cell with 40 Å-thick tunnel oxide erased by Fowler-Nordheim (FN) tunneling of hole. Thanks to introducing high-k dielectrics, alumina (Al2O3) as a blocking oxide, the erase threshold voltage can be maintained to less than - 3.0 V, meaning hole-trapping in SiN. We extracted the nitride trap densities of electron and hole for the TANOS cell. It is demonstrated that the TANOS structure is very available to investigate the trap density with shallower energy. The energy level of hole trap (1.28 eV) is found to be deeper than that of electron (0.8 eV). As the cycling stress is performed, persistent hole-trapping is observed unlike endurance characteristics of conventional floating-gate cell. The hole trapping during the cycling stress can be attributed to two possibilities. The injected holes are trapped in neutral trap of tunnel oxide and residue of holes which is not somewhat compensated by injected electrons may be accumulated in SiN. It is demonstrated the erase operation of the TANOS cell is governed by Fowler-Nordheim tunneling of hole due to the field concentration across the tunnel oxide.

scholarly journals Radiation Tolerance and Charge Trapping Enhancement of ALD HfO2/Al2O3 Nanolaminated Dielectrics

Materials ◽  
2021 ◽  
Vol 14 (4) ◽  
pp. 849
Author(s):  
Dencho Spassov ◽  
Albena Paskaleva ◽  
Elżbieta Guziewicz ◽  
Vojkan Davidović ◽  
Srboljub Stanković ◽  
...  
Keyword(s):  
Charge Trapping ◽  
Atomic Layer ◽  
Information Storage ◽  
Radiation Tolerance ◽  
Leakage Currents ◽  
High K ◽  
60Co Source ◽  
Retention Characteristics ◽  
High K Materials ◽  
High K Dielectric

High-k dielectric stacks are regarded as a promising information storage media in the Charge Trapping Non-Volatile Memories, which are the most viable alternative to the standard floating gate memory technology. The implementation of high-k materials in real devices requires (among the other investigations) estimation of their radiation hardness. Here we report the effect of gamma radiation (60Co source, doses of 10 and 10 kGy) on dielectric properties, memory windows, leakage currents and retention characteristics of nanolaminated HfO2/Al2O3 stacks obtained by atomic layer deposition and its relationship with post-deposition annealing in oxygen and nitrogen ambient. The results reveal that depending on the dose, either increase or reduction of all kinds of electrically active defects (i.e., initial oxide charge, fast and slow interface states) can be observed. Radiation generates oxide charges with a different sign in O2 and N2 annealed stacks. The results clearly demonstrate a substantial increase in memory windows of the as-grown and oxygen treated stacks resulting from enhancement of the electron trapping. The leakage currents and the retention times of O2 annealed stacks are not deteriorated by irradiation, hence these stacks have high radiation tolerance.

Nonvolatile memory MOS capacitors made of CdSe embedded ZrHfO high-k gate dielectric

2013 ◽  
Vol 1562 ◽  
Author(s):  
Chi-Chou Lin ◽  
Yue Kuo
Keyword(s):  
Gate Voltage ◽  
Coulomb Blockade ◽  
Nonvolatile Memory ◽  
Gate Dielectric ◽  
Stress Test ◽  
Charge Trapping ◽  
Differential Resistance ◽  
Mos Capacitors ◽  
Mos Capacitor ◽  
High K

ABSTRACTMOS capacitor composed of nc-CdSe embedded ZrHfO high-k gate dielectric stack was fabricated and characterized for nonvolatile memory functions. Detailed material and electrical properties have been investigated. With a large charge trapping capability, this kind of device can trap electrons or holes depending on the polarity and magnitude of the applied gate voltage. For the same stress time, the device trapped more holes than electrons under the same magnitude of gate voltage but different polarity. The negative differential resistance peak was observed at the room temperature due to the Coulomb blockade effect. The charge trapping mechanism was delineated with the constant voltage stress test. After 10 years of storage, about 56% of trapped charges still remain in the device.

Nonvolatile memories based on AlOx embedded ZrHfO high-k gate dielectric

2014 ◽  
Vol 1691 ◽  
Author(s):  
Shumao Zhang ◽  
Yue Kuo ◽  
Xi Liu ◽  
Chi-Chou Lin
Keyword(s):  
Gate Dielectric ◽  
Dielectric Structure ◽  
Mos Capacitors ◽  
Hole Trapping ◽  
Nonvolatile Memories ◽  
High K ◽  
Positive Voltage ◽  
Voltage Dependent ◽  
Trapping Process ◽  
Negative Gate Voltage

ABSTRACTMOS capacitors with the ZrHfO/AlOx/ZrHfO high-k gate dielectric stack were prepared and characterized for memory functions. The device prefers to trap holes, i.e., under the negative gate voltage, rather than electrons, i.e., under the positive voltage. The hole-trapping process is time and voltage dependent. The weakly trapped holes are quickly released upon the remove of the stress voltage. However, more than 30% of the originally trapped holes can be retained in the device after 10 years. The AlOx embedded ZrHfO high-k stack is a suitable gate dielectric structure for nonvolatile memories.

High-k MNOS-Like Stacked Dielectrics for Non-Volatile Memory Application

2016 ◽  
Vol 39 ◽  
pp. 121-133
Author(s):  
Larysa Khomenkova ◽  
Pascal Normand ◽  
Fabrice Gourbilleau ◽  
Abdelilah Slaoui ◽  
Caroline Bonafos
Keyword(s):  
Electrical Characterization ◽  
Charge Trapping ◽  
Flat Band ◽  
Carrier Injection ◽  
High K ◽  
Structural And Electrical Properties ◽  
Non Volatile Memory ◽  
High Resolution Tem ◽  
Mis Capacitors ◽  
Dielectric Structures

Charge-trapping memories such as SONOS and MONOS have attracted considerable attention as promising alternatives for next-generation flash memories due to dielectric layer’s scalability, process simplicity, power economy, operation versatility. Nevertheless, the continued miniaturization of the devices forces an application of high-k dielectrics. In this work high-k stacked dielectric structures based on the combination of Hf-based and SiNx materials were fabricated. Their structural and electrical properties versus deposition conditions are studied by means of FTIR-ATR and high-resolution TEM techniques. All samples demonstrated smooth surface (roughness below 1 nm) and abrupt interfaces between the different stacked layers. No crystallization of Hf-based layers was observed after annealing at 800°C for 30 min, demonstrating their amorphous nature and phase stability upon annealing. Electrical characterization was carried out for all samples through capacitance-voltage (C-V) measurements of MIS capacitors. Uniform C-V characteristics were measured along the samples for all stacks. Besides, significant flat-band hysteresis due to charging of the stacks caused by carrier injection from the substrate was observed for the structures with pure HfO2 layers.

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