Defect Reduction and Defect Engineering in Silicon-on-Sapphire Material Using Ge Implantation

1990 ◽  
Vol 201 ◽  
Author(s):  
F. Namavar ◽  
E. Cortesi ◽  
N. M. Kalkhoran ◽  
J. M. Manke ◽  
B. L. Buchanan
Keyword(s):  
Leakage Current ◽  
Defect Density ◽  
Solid Phase ◽  
Substantial Reduction ◽  
Interface Region ◽  
Radiation Environment ◽  
Solid Phase Epitaxy ◽  
Defect Reduction ◽  
Radiation Induced

AbstractSubstantial reduction of defect density in silicon-on-sapphire (SOS) material is required to broaden its range of applications to include CMOS and bipolar devices. In recent years, solid phase epitaxy and regrowth (SPEAR) and double solid phase epitaxy (DSPE) processes were applied to SOS to reduce the density of defects in the silicon. These methods result in improved carrier mobilities, but also in increased leakage current, even before irradiation. In a radiation environment, this material has a large increase in radiation induced back channel leakage current as compared to standard wafers. In other words, the radiation hardness quality of the SOS declines when the crystalline quality of the Si near the sapphire interface is improved.In this paper, we will demonstrate that Ge implantation, rather than Si implantation normally employed in DSPE and SPEAR processes, is an efficient and more effective way to reduce the density of defects near the surface silicon region without improving the Si/sapphire interface region. Ge implantation may be used to engineer defects in the Si/sapphire interface region to eliminate back channel leakage problems.

Optimising the Growth of Few-Layer Graphene on Silicon Carbide by Nickel Silicidation

2013 ◽  
Vol 740-742 ◽  
pp. 121-124 ◽  
Author(s):  
Enrique Escobedo-Cousin ◽  
Konstantin Vassilevski ◽  
Toby Hopf ◽  
Nick G. Wright ◽  
Anthony O’Neill ◽  
...  
Keyword(s):  
Photoelectron Spectroscopy ◽  
Solid Phase ◽  
Sample Surface ◽  
Device Fabrication ◽  
Solid Phase Epitaxy ◽  
X Ray ◽  
Graphene Films ◽  
Few Layer Graphene ◽  
The Impact

Few-layers graphene films (FLG) were grown by local solid phase epitaxy on a semi-insulating 6H-SiC substrate by annealing Ni films deposited on the Si and C-terminated faces of the SiC. The impact of the annealing process on the final quality of the FLG films is studied using Raman spectroscopy. X-ray photoelectron spectroscopy was used to verify the presence of graphene on the sample surface. We also demonstrate that further device fabrication steps such as dielectric deposition can be carried out without compromising the FLG films integrity.

Approaches For Reduction Of The Defect Density In Group III Nitride Based Heterostructures

2000 ◽  
Vol 639 ◽  
Author(s):  
T. S. Zheleva ◽  
F. Karoui ◽  
K. Kirchner ◽  
M. Derenge ◽  
K. A. Jones ◽  
...  
Keyword(s):  
Defect Density ◽  
Solid Phase ◽  
Growth Direction ◽  
Stress Distributions ◽  
Free Standing ◽  
Defect Reduction ◽  
Group Iii ◽  
Grain Boundary Mobility ◽  
And Migration ◽  
Group Iii Nitride

ABSTRACTLateral epitaxial overgrowth (LEO), pendeo-epitaxy (PE), and solid-phase epitaxial recrystallization (SPER) are discussed as three approaches for reducing the defect density in group III nitride based heterostructures. Studies of the LEO GaN and PE GaN revealed, that a major factor for the defect reduction in the laterally overgrown regions is the change of the dominant growth direction - from vertical in the window regions to lateral in the regions over the mask or over the trenches, and the related threading dislocations lines redistribution. The mechanisms of defect reduction in LEO GaN and PE GaN are similar, although they arise through different process routes, and are related to the free-standing (PE) or quasi-free-standing (LEO) growth of GaN, and the associated stress redistribution. The stress distributions in the LEO and PE GaN heterostructures are calculated and compared with finite element modeling. Another approach for reduction of the defects is the SPER process and the related thermal activation for dislocation reactions and grain boundary mobility and migration. This approach is shown in the example of annealed AlN films.

Challenges for Improving the Crystal Quality of 3C-SiC Verified with MOSFET Performance

2008 ◽  
Vol 600-603 ◽  
pp. 89-94 ◽  
Author(s):  
Hiroyuki Nagasawa ◽  
Kuniaki Yagi ◽  
Takamitsu Kawahara ◽  
Naoki Hatta ◽  
Masayuki Abe ◽  
...  
Keyword(s):  
Epitaxial Growth ◽  
Leakage Current ◽  
Hybrid Electric Vehicle ◽  
Reduction Method ◽  
Defect Density ◽  
Motor Drives ◽  
Power Electronic ◽  
Surface Polarity ◽  
Blocking Voltage

In 3C-SiC MOSFETs, planar defects like anti-phase boundaries (APBs) and stacking-faults (SFs) reduce the breakdown voltage and induce leakage current. Although the planar defect density can be reduced by growing 3C-SiC on undulant-Si substrate, specific type of SFs, which expose the Si-face, remains on the (001) surface. Those SFs increase the leakage current in devices made with 3C-SiC. In order to eliminate the residual SFs, an advanced SF reduction method involving polarity conversion and homo-epitaxial growth was developed. This method is called switch-back epitaxy (SBE) and consists of the conversion of the SF surface polarity from Si-face to C-face and following homo-epitaxial growth. The reduction of the SF density in SBE 3C-SiC results in a tremendous improvement of the device performance. The combination of the achieved blocking voltage with the demonstrated high current capability indicates the potential of 3C-SiC vertical MOSFETs for high and medium power electronic applications such as electric and hybrid electric vehicle (EV/HEV) motor drives.

Process and Mechanism of CoSi2/Si Solid Phase Epitaxy by Multilayer Reaction

1999 ◽  
Vol 580 ◽  
Author(s):  
Bing-Zong Li ◽  
Xin-Ping Qu ◽  
Guo-Ping Ru ◽  
Ning Wang ◽  
Paul Chu
Keyword(s):  
Epitaxial Growth ◽  
Solid Phase ◽  
Amorphous Layer ◽  
Solid Phase Epitaxy ◽  
Initial Stage ◽  
Vital Effect ◽  
Amorphous Si ◽  
Kinetics Of ◽  
State Amorphization

AbstractA multilayer structure of Co/a-Si/Ti/Si(100) together with Co/Ti/Si(100) is applied to investigate the process and mechanism of CoSi2 epitaxial growth on a Si(100) substrate. The experimental results show that by adding an amorphous Si layer with a certain thickness, the epitaxial quality of CoSi2 is significantly improved. A multi-element amorphous layer is formed by a solid state amorphization reaction at the initial stage of the multilayer reaction. This layer acts as a diffusion barrier, which controls the atomic interdiffusion of Co and Si and limits the supply of Co atoms. It has a vital effect on the multilayer reaction kinetics, and the epitaxial growth of CoSi2 on Si. The kinetics of the CoSi2 growth process from multilayer reactions is investigated.

Growth of Epitaxial CoSi2/Si Multilayers

1986 ◽  
Vol 77 ◽  
Author(s):  
B. D. Runt ◽  
N. Lewis ◽  
L. J. Schotalter ◽  
E. L. Hall ◽  
L. G. Turner
Keyword(s):  
Electron Microscopy ◽  
Transmission Electron Microscopy ◽  
Room Temperature ◽  
Solid Phase ◽  
Multilayer Structures ◽  
Solid Phase Epitaxy ◽  
Cross Sectional ◽  
Temperature Growth ◽  
Transmission Electron

ABSTRACTEpitaxial CoSi2/Si multilayers have been grown on Si(111) substrates with up to four bilayers of suicide and Si. To our knowledge, these are the first reported epitaxial metal-semiconductor multilayer structures. The growth of these heterostructures is complicated by pinhole formation in the suicide layers and by nonuniform growth of Si over the suicide films, but these problems can be controlled through nse of proper growth techniques. CoSi2 pinhole formation has been significantly reduced by utilizing a novel solid phase epitaxy technique in which room-temperature-deposited Co/Si bilayers are annealed to 600–650δC to form the suicide layers. Islanding in the Si layers is minimized by depositing a thin (<100Å) Si layer at room temperature with subsequent high temperature growth of the remainder of the Si. Cross-sectional transmission electron microscopy studies demonstrate that these growth procedures dramatically improve the continuity and quality of the CoSi. and Si multilayers.

High-Quality Boron and BF2+-Implanted P+ Junctions in Si Using Solid Phase Epitaxy and Transient Annealing

1984 ◽  
Vol 35 ◽  
Author(s):  
P.K. Vasudev ◽  
A.E. Schmitz ◽  
G.L. Olson
Keyword(s):  
Solid Phase ◽  
Solid Phase Epitaxy ◽  
Impurity Effects ◽  
Solid Phase Crystallization ◽  
High Quality ◽  
Time Resolved ◽  
Boron Doped ◽  
Epitaxial Regrowth ◽  
Doping Profiles

ABSTRACTWe report on a systematic study of the doping profiles resulting from rapid thermal annealing of boron and BF2+-implanted silicon samples that were preamorphized by Si+ implantation. A two-step process consisting of an initial solid phase epitaxial regrowth followed by a brief (~5 sec) high temperature (1050ଌ) anneal produces extremely shallow (<1500Å) junctions with low defect concentrations. The quality of the epitaxial regrowth is very sensitive to implant conditions and impurity effects as deduced from time-resolved reflectivity measurements. Using the best conditions for implantation and solid phase crystallization, we have obtained boron-doped regions with sheet resistivities of 40 Ω/ and BF2-doped regions of resistivity 60 Ω/.

scholarly journals Surface-Interface Quality of Mn5Ge3 Thin Films on Ge(001): Reactive Deposition Epitaxy vs. Solid Phase Epitaxy

2018 ◽  
Vol 24 (S1) ◽  
pp. 1622-1623 ◽  
Author(s):  
Adriana Alvídrez-Lechuga ◽  
José T. Holguín-Momaca ◽  
Óscar O. Solís-Canto ◽  
Carlos R. Santillán-Rodríguez ◽  
José A. Matutes-Aquino ◽  
...  
Keyword(s):  
Thin Films ◽  
Solid Phase ◽  
Solid Phase Epitaxy ◽  
Interface Quality ◽  
Reactive Deposition

Progress in Large-Area 4H-SiC Epitaxial Layer Growth in a Warm-Wall Planetary Reactor

2014 ◽  
Vol 778-780 ◽  
pp. 103-108 ◽  
Author(s):  
Bernd Thomas ◽  
Darren M. Hansen ◽  
Jie Zhang ◽  
Mark J. Loboda ◽  
Junichi Uchiyama ◽  
...  
Keyword(s):  
Epitaxial Layer ◽  
Defect Density ◽  
Layer Growth ◽  
Power Devices ◽  
Large Area ◽  
Defect Reduction ◽  
Mean Values ◽  
Bipolar Devices ◽  
Thickness Measurements

Results are presented for epitaxial SiC layers grown on 100 mm and 150 mm wafers suitable for power devices by CVD using a VP2800WW multi-wafer reactor with 10×100mm and 6×150mm configurations. We have demonstrated continuous improvement in uniformity for thickness and doping, as well as in defect reduction in standard epitaxy on 100 mm wafers. Thickness and doping sigma/mean values of <1.5% and <8%, respectively, could be routinely achieved. Doping and thickness measurements of 30 μm layer growth show results similar to standard epilayer growth. The averaged projected site yields of 80% for 5x5 mm2 and of 96% for 2x2 mm2 correspond to a low epitaxial defect density of <1 cm="" sup="">-2 in 30μm thick epilayers. Epilayer structures for bipolar devices like PiN diodes and BJTs are shown. The interface regions between nitrogen doped and aluminum doped layers show an abrupt transition of dopant concentration. Wafer quality of 100 mm and 150 mm material is presented as an important base factor for excellent epitaxial layer quality. It is shown that 150 mm substrates exhibit TSD and BPD densities very similar to the 100 mm materials. Site counts for TSDs and BPDs on sample wafers show dislocations densities of 500 cm-2 and 300 cm-2, respectively. After CVD process optimization, a thickness uniformity (sigma/mean) of <1.5% and a doping uniformity of <13% was achieved on epitaxial layers on 150mm.

Low-Temperature Solid-Phase Epitaxy of Defect-Free Aluminum p+-doped Silicon for Nanoscale Device Applications

2006 ◽  
Vol 940 ◽  
Author(s):  
Yann Civale ◽  
Lis K. Nanver ◽  
Peter Hadley ◽  
Egbert J. G. Goudena ◽  
Henk W. van Zeijl ◽  
...  
Keyword(s):  
Solid Phase ◽  
Bipolar Junction Transistors ◽  
Solid Phase Epitaxy ◽  
Electrical Characteristics ◽  
Nanoscale Device ◽  
Experimental Conditions ◽  
Whole Process ◽  
Device Applications ◽  
Nm Range

ABSTRACTA solid phase epitaxy (SPE) technique was developed to grow p+ aluminum-doped crystalline Si in a fully CMOS compatible process. This paper describes the experimental conditions leading to the selective growth of nanoscale single crystals where the location and dimensions are well controlled, even in the sub-100 nm range. The SPE Si crystals are defined by conventional lithography, show excellent electrical characteristics, and are uniform over the whole wafer. Fifty nanometer thick p+ SPE Si crystals were used to fabricate p+-n diodes and p+-n-p bipolar junction transistors. The high quality of the SPE Si and the remarkable control of the whole process, even in the sub-100 nm range, make this module directly usable for Si-based nanodevices.

Sign in / Sign up

Export Citation Format

Share Document