Transient Annealing of Boron Implanted Devices

1983 ◽  
Vol 23 ◽  
Author(s):  
S. R. Wilson ◽  
W. M. Paulson ◽  
C. J. Varker ◽  
A. Lowe ◽  
R. B. Gregory ◽  
...  

ABSTRACTShallow-junction semiconductor devices have been fabricated using ion implantation and transient annealing with a Varian IA-200 isothermal annealer. Boron implanted diodes, npn bipolar transistors and CMOS ring oscillators have been fabricated and are compared to furnace annealed devices. Boron implanted diodes have been annealed with the RIA and yield acceptably low leakage currents, comparable to furnace annealed devices. The RIA devices have recombination lifetimes of ∼10 μsec. The bipolar transistors subjected to a transient anneal have good base-collector and emitterbase junctions as well as gains of ∼100 in good agreement with the design of the device. MOSFETs and CMOS ring oscillators were fabricated using self-aligned polysilicon gates. The transient annealed devices were equal or superior to devices which were furnace annealed at 800°C for 10 min. The low temperature furnace anneal was necessary to minimize short channel effects. The transient anneal resulted in ring oscillators which were a factor of two faster than furnace samples that were annealed.

Persistent scaling of planar MOSFET results in increase in transistor package density and performance of chip. However at nanometer regime , it has become a very challenging issue due to the increase in the short channel effects. In nanoscaled MOSFETs, the channel loses control from gate terminal due to potential at drain. Due to this, it is difficult to turn off MOSFET completely which inturn leads to leakage currents. Since cache memory occupies more area of processors, it is difficult to reduce leakage power in microprocessors. Double gate transistors have become replacement for MOS transistors at nano level. Since FINFETs have double gates, the leakage currents can be controlled effectively than planar MOSFET. In this paper, leakage currents of 6T & 7T-SRAM memory cell are analyzed using FINFETs at 22nm technology in hspice software


1993 ◽  
Vol 3 (9) ◽  
pp. 1719-1728
Author(s):  
P. Dollfus ◽  
P. Hesto ◽  
S. Galdin ◽  
C. Brisset

2007 ◽  
Vol 54 (8) ◽  
pp. 1943-1952 ◽  
Author(s):  
A. Tsormpatzoglou ◽  
C.A. Dimitriadis ◽  
R. Clerc ◽  
Q. Rafhay ◽  
G. Pananakakis ◽  
...  

1989 ◽  
Vol 36 (3) ◽  
pp. 522-528 ◽  
Author(s):  
S. Veeraraghavan ◽  
J.G. Fossum

MOSFET have been scaled down over the past few years in order to give rise to high circuit density and increase the speed of circuit. But scaling of MOSFET leads to issues such as poor control gate over the current which depends on gate voltage. Many short channel effects (SCE) influence the circuit performance and leads to the indeterminist response of drain current. These effects can be decreased by gate excitation or by using multiple gates and by offering better control gate the device parameters. In Single gate MOSFET, gate electric field decreases but multigate MOSFET or FinFET provides better control over drain current. In this paper, different FET structures such as MOSFET, TFET and FINFET are designed at 22nm channel length and effect of doping had been evaluated and studied. To evaluate the performance donor concentration is kept constant and acceptor concentration is varied.


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