Structure Of The Defects Responsible For B-Mode Breakdown Of Gate Oxide Grown On The Surface Of Silicon Wafers

1996 ◽  
Vol 442 ◽  
Author(s):  
T. Mera ◽  
J. Jablonski ◽  
M. Danbata ◽  
K. Nagai ◽  
M. Watanabe
Keyword(s):  
Gate Oxide ◽  
Wafer Surface ◽  
Cross Sectional ◽  
Oxide Breakdown ◽  
Breakdown Mechanism ◽  
Transmission Electron ◽  
Thermal Oxide ◽  
Before And After ◽  
Thick Oxide Layer ◽  
Unambiguous Detection

AbstractCrystal-originated pits are known as the defects responsible for B-mode Time Zero Dielectric Break-down (TZDB) of the gate oxide grown on the surface of Si wafers. In order to clarify the breakdown mechanism, we have analyzed the structure of those defects formed at the surface of bare and oxidized wafers. In the latter case the analysis has been done both before and after gate oxide breakdown. Electric breakdown has been accomplished by Cu decoration method, recognized as an effective tool for unambiguous detection and positioning of the defects causing B-mode TZDB. As revealed by cross-sectional transmission electron microscopy (XTEM), crystal-originated pits at the bare wafer surface are polyhedral pits having about 5-nm-thick oxide layer on the inner walls. During gate oxidation the thermal oxide is growing faster on the pit walls than on the wafer surface, except for the pit comers where the oxide thinning has been observed. Resulting concave comers of the oxidized pits are suggested to be the weak spots where B-mode TZDB occurs.

Relation between Defects on 4H-SiC Epitaxial Surface and Gate Oxide Reliability

2013 ◽  
Vol 740-742 ◽  
pp. 745-748 ◽  
Author(s):  
J. Sameshima ◽  
Osamu Ishiyama ◽  
Atsushi Shimozato ◽  
K. Tamura ◽  
H. Oshima ◽  
...  
Keyword(s):  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Wafer Surface ◽  
Cross Sectional ◽  
Mos Capacitors ◽  
Oxide Breakdown ◽  
Time Dependent Dielectric Breakdown ◽  
Oxide Reliability ◽  
Breakdown Region

Time-dependent dielectric breakdown (TDDB) measurement of MOS capacitors on an n-type 4 ° off-axis 4H-SiC(0001) wafer free from step-bunching showed specific breakdown in the Weibull distribution plots. By observing the as-grown SiC-epi wafer surface, two kinds of epitaxial surface defect, Trapezoid-shape and Bar-shape defects, were confirmed with confocal microscope. Charge to breakdown (Qbd) of MOS capacitors including an upstream line of these defects is almost the same value as that of a Wear-out breakdown region. On the other hand, the gate oxide breakdown of MOS capacitors occurred at a downstream line. It has revealed that specific part of these defects causes degradation of oxide reliability. Cross-sectional TEM images of MOS structure show that gate oxide thickness of MOS capacitor is non-uniform on the downstream line. Moreover, AFM observation of as-grown and oxidized SiC-epitaxial surfaces indicated that surface roughness of downstream line becomes 3-4 times larger than the as-grown one by oxidation process.

Strain Relaxation in GaAs on Si by Two Groups of Misfit Dislocations

1995 ◽  
Vol 399 ◽  
Author(s):  
M. Tamura ◽  
T. Saitoh ◽  
T. Yodo
Keyword(s):  
Strain Relaxation ◽  
Lattice Misfit ◽  
Misfit Dislocations ◽  
Cross Sectional ◽  
Plan View ◽  
Partial Dislocations ◽  
Group I ◽  
Transmission Electron ◽  
Before And After ◽  
Gaas Films

ABSTRACTHigh-resolution cross-sectional and conventional plan-view transmission electron microscope observations have been carried out for molecular beam epitaxially grown GaAs films on vicinal Si (001) as a function of film thicknesses and observation directions between two orthogonal <110> directions before and after annealing. Two groups of misfit dislocations are characterized by analyzing whether their extra half planes exist in the film and the substrate side. The group I misfit dislocations due to a stress caused by a lattice misfit between GaAs and Si consist of partial and, 60° and 90° complete dislocations in an as-grown state. After annealing partial dislocations almost disappear and 90° perfect dislocations are predominantly observed. The group II misfit dislocations due to a thermal-expansion misfit-induced stress are all of the 60° type complete dislocations, independent of film thickness and annealing.

Influence of Threading Dislocations on Lifetime of Gate Thermal Oxide

2012 ◽  
Vol 717-720 ◽  
pp. 477-480 ◽  
Author(s):  
Kensaku Yamamoto ◽  
M. Nagaya ◽  
H. Watanabe ◽  
E. Okuno ◽  
T. Yamamoto ◽  
...  
Keyword(s):  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Crystal Defects ◽  
Gate Oxides ◽  
Time Dependent Dielectric Breakdown ◽  
Transmission Electron ◽  
Thermal Oxide ◽  
Order Of Magnitude ◽  
The Relationship ◽  
Exact Relationship

The reliability of gate oxides is a fundamental issue for realizing SiC MOSFETs. Many reports said that crystal defects shorten the lifetime of the gate oxide. And, epi defects, the basal plane dislocations and threading screw dislocations (TSD) are considered killer defects. However, because of the high TSD density of commercial SiC wafers, the exact relationship between other kinds of dislocations with lifetime has not been revealed. On the other hand, RAF wafers that we developed have low TSD density, so it is easy to evaluate the relationship between other kinds of dislocations and lifetime. By using RAF wafers, in this study, we clarified the relationship between the lifetime of the gate oxide and crystal defects. We fabricated MOS diodes and measured their lifetimes by TDDB (Time Dependent Dielectric Breakdown) measurement. The breakdown points were defined by the photo-emission method. Finally, we classified the defects by TEM (Transmission Electron Microscopy). As the results, it was clarified that threading edge dislocation (TED) decreases the lifetime as does TSD, which earlier reports said. The lifetime of the gate oxide area, in which a TED is included, was shorter by one order of magnitude than a wear-out breakdown. And, the TSD was two orders.

Structural Characterization of Prismatic Stacking Faults of Two Types of Carrot Defects in 4H-SiC Epi Wafers

2020 ◽  
Vol 1004 ◽  
pp. 421-426
Author(s):  
Hideki Sako ◽  
Kentaro Ohira ◽  
Kenji Kobayashi ◽  
Toshiyuki Isshiki
Keyword(s):  
Electron Microscopy ◽  
Transmission Electron Microscopy ◽  
Stacking Faults ◽  
Wafer Surface ◽  
Cross Sectional ◽  
Force Microscopy ◽  
Atomic Force ◽  
Transmission Electron ◽  
Scanning Transmission ◽  
The Difference

Two types of carrot defects with and without a shallow pit were found by mirror projection electron microscopy (MPJ) inspection in 4H-SiC epi wafer. Surface morphology and cross-sectional structure of prismatic stacking faults (PSFs) were investigated using MPJ and atomic force microscopy (AFM), transmission electron microscopy (TEM) and high-resolution scanning transmission electron microscopy (STEM). The depths of the surface grooves due to the PSFs, the stacking sequences around the PSFs and the structure of the Frank-type stacking faults which were connected to the PSFs were different. We discuss the difference between the two types of carrot defects.

Cross-Sectional TEM Study of Three-Dimensional MOS Devices

1987 ◽  
Vol 107 ◽  
Author(s):  
Kyung-Ho Park ◽  
T. Sasaki ◽  
T. Iwai ◽  
M. Hasegawa ◽  
N. Sasaki
Keyword(s):  
Electron Microscopy ◽  
Three Dimensional ◽  
Gate Oxide ◽  
Crystal Defects ◽  
Interface Roughness ◽  
Bulk Silicon ◽  
Cross Sectional ◽  
Mos Devices ◽  
Transmission Electron ◽  
20 Nm

AbstractThis paper describes cross-sectional transmission electron microscopy (TEM) observation on finished 3-D MOS devices, fabricated with a laser-recrystallized SOI. The laser-recrystallized SOI contained crystal defects such as micro-twinning, grain boundaries and dislocations. It is also clearly shown that the interface roughness between the gate oxide and SOI is as much as 20 nm height, in where the interface is very smooth between the gate oxide and bulk silicon.

Characterization of SiGe Layer on Insulator by In-Plane Diffraction Method

2005 ◽  
Vol 108-109 ◽  
pp. 451-456
Author(s):  
M. Imai ◽  
Y. Miyamura ◽  
D. Murata ◽  
A. Ogi
Keyword(s):  
Diffraction Method ◽  
Sige Layer ◽  
Wafer Surface ◽  
Process Conditions ◽  
Cross Sectional ◽  
Lattice Constants ◽  
Smooth Interface ◽  
Transmission Electron ◽  
Out Of Plane ◽  
Plane Diffraction

Four types of SGOI (SiGe on Insulator) wafers were fabricated by the combination of SiGe epitaxial growth, SIMOX (Separation by Implanted Oxygen) processes and oxidation. By the cross-sectional TEM (Transmission Electron Microscopy) and EDS (Energy Dispersive Spectroscopy), it is confirmed that each wafer has smooth interface between a top layer (Si or SiGe) and a BOX (buried oxide) layer and Ge atoms in SiGe layer distribute homogeneously for SGOI_A and SGOI_B. Using high-resolution X-ray diffractometry, the crystallographic properties of SiGe layer are characterized with in-plane and out of plane diffraction methods. The lattice constants are calculated for the planes of perpendicular and parallel to wafer surface and the degree of relaxation are estimated for the SiGe layer of each wafer. The rocking curve measurements reveal that the lattice turbulence of SiGe layer is influenced by SIMOX process conditions, Ge content and the layer thickness.

TDDB Measurement of Gate SiO2 on 4H-SiC Formed by Chemical Vapor Deposition

2008 ◽  
Vol 600-603 ◽  
pp. 799-802 ◽  
Author(s):  
Keiko Fujihira ◽  
Shohei Yoshida ◽  
Naruhisa Miura ◽  
Yukiyasu Nakao ◽  
Masayuki Imaizumi ◽  
...  
Keyword(s):  
Chemical Vapor Deposition ◽  
Vapor Deposition ◽  
Chemical Vapor ◽  
Gate Oxide ◽  
Thermally Grown Oxide ◽  
Oxide Breakdown ◽  
Thermal Oxide ◽  
Field Oxide ◽  
Thermally Grown

The reliability of CVD gate oxide was investigated by CCS-TDDB measurement and compared with thermally grown gate oxide. Although the QBD of thermal oxide becomes smaller for the larger oxide area, the QBD of CVD oxide is almost independent of the investigated gate oxide area. The QBD at F = 50% of CVD oxide, 3 C/cm2, is two orders of magnitude larger for the area of 1.96×10-3 cm2 at 1 mA/cm2 compared to that of thermal oxide. More than 80% of the CVD oxide breakdown occurs at the field oxide edge and more than 70% of the thermal oxide breakdown in the inner gate area. These results suggest that the lifetime of CVD oxide is hardly influenced by the quality of SiC, while the defects and/or impurities in SiC affect the lifetime of thermally grown oxide.

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