Simulational study for gate oxide breakdown mechanism due to non-uniform electron current flow

Author(s):  
M. Kubota ◽  
K. Harafuji ◽  
A. Misaka ◽  
A. Yamano ◽  
H. Nakagawa ◽  
...  
1996 ◽  
Vol 442 ◽  
Author(s):  
T. Mera ◽  
J. Jablonski ◽  
M. Danbata ◽  
K. Nagai ◽  
M. Watanabe

AbstractCrystal-originated pits are known as the defects responsible for B-mode Time Zero Dielectric Break-down (TZDB) of the gate oxide grown on the surface of Si wafers. In order to clarify the breakdown mechanism, we have analyzed the structure of those defects formed at the surface of bare and oxidized wafers. In the latter case the analysis has been done both before and after gate oxide breakdown. Electric breakdown has been accomplished by Cu decoration method, recognized as an effective tool for unambiguous detection and positioning of the defects causing B-mode TZDB. As revealed by cross-sectional transmission electron microscopy (XTEM), crystal-originated pits at the bare wafer surface are polyhedral pits having about 5-nm-thick oxide layer on the inner walls. During gate oxidation the thermal oxide is growing faster on the pit walls than on the wafer surface, except for the pit comers where the oxide thinning has been observed. Resulting concave comers of the oxidized pits are suggested to be the weak spots where B-mode TZDB occurs.


1999 ◽  
Vol 592 ◽  
Author(s):  
M. F. Li ◽  
Y. D. He ◽  
S. G. Ma ◽  
Byung Jin Cho ◽  
K. F. Lo

ABSTRACTIn this work, we report the link between the primary hot hole and Fowler Nordheim (FN) electron injections in oxide breakdown mechanism. A simple breakdown model is established. The experimental method is carefully designed to measure the primary hot hole fluence and FN electron fluence separately and accurately. The calculation based on our model is in very good agreement with our experiments. Oxide breakdown is stimulated by a combined effect when the sum of the trap density Dpri activated by primary hot hole injection and the trap density Dn activated by FN electron injection reaches a critical value Dcri. The hole is two orders of magnitude more effective than FN electron in causing breakdown. Since primary hot hole injection may occurs under many realistic device operation in the circuit, existing oxide lifetime projected from conventional TDDB measurement by only applying FN stress is overestimated in many cases. The model demonstrated in this work lays the groundwork in approaching a more appropriate way for predicting the oxide reliability and lifetime.


Author(s):  
K.A. Mohammad ◽  
L.J. Liu ◽  
S.F. Liew ◽  
S.F. Chong ◽  
D.G. Lee ◽  
...  

Abstract The paper focuses on the pad contamination defect removal technique. The defect is detected at the outgoing inspection step. The failure analysis results showed that the defect is Fluorine type contamination. The failure analysis indicated many source contributors mainly from Fluorine based processes. The focus is in the present work is in the rework method for the removal of this defect. The combination of wet and dry etch processing in the rework routine is utilized for the removal of the defect and preventive action plans for in-line were introduced and implemented to avoid this event in the future. The reliability of the wafer is verified using various tests including full map electrical, electrical sort, gate oxide breakdown (GOI) and wafer reliability level, passivation quick kill to ensure the integrity of the wafer after undergoing the rework routine. The wafer is monitored closely over a period of time to ensure it has no mushroom defect.


Author(s):  
Nobuyuki Wakai ◽  
Yuji Kobira ◽  
Hidemitsu Egawa ◽  
Masayoshi Tsutsumi

Abstract Fundamental consideration for CDM (Charged Device Model) breakdown was investigated with 90nm technology products and others. According to the result of failure analysis, it was found that gate oxide breakdown was critical failure mode for CDM test. High speed triggered protection device such as ggNMOS and SCR (Thyristor) is effective method to improve its CDM breakdown voltage and an improvement for evaluated products were confirmed. Technological progress which is consisted of down-scaling of protection device size and huge number of IC pins of high function package makes technology vulnerable and causes significant CDM stress. Therefore, it is expected that CDM protection designing tends to become quite difficult. In order to solve these problems in the product, fundamental evaluations were performed. Those are a measurement of discharge parameter and stress time dependence of CDM breakdown voltage. Peak intensity and rise time of discharge current as critical parameters are well correlated their package capacitance. Increasing stress time causes breakdown voltage decreasing. This mechanism is similar to that of TDDB for gate oxide breakdown. Results from experiences and considerations for future CDM reliable designing are explained in this report.


2001 ◽  
Vol 59 (1-4) ◽  
pp. 155-160 ◽  
Author(s):  
B Kaczer ◽  
R Degraeve ◽  
A De Keersgieter ◽  
M Rasras ◽  
G Groeseneken

2005 ◽  
Vol 863 ◽  
Author(s):  
C. L. Gan ◽  
C. Y. Lee ◽  
C. K. Cheng ◽  
J. Gambino

AbstractThe reliability of Cu M1-V1-M2-V2-M3 interconnects with SiN and CoWP cap layers was investigated. Similar to previously reported results, the reliability of CoWP capped structures is much better than identical SiN capped structures. However, it was also observed that the reliability of CoWP capped interconnects was independent of the direction of electrical current flow. This phenomenon is different from what was observed for SiN capped structures, where M2 lines with electron current flow in the upstream configuration (“via-below”) have about three times larger median-time-to-failure than identical lines in the downstream configuration (“viaabove”). This is because the Cu/SiN interface is the preferential void nucleation site and provides the fastest diffusion pathway in such an architecture. Failure analysis has shown that fatal partially-spanned voids usually had formed directly below the via for “via-above” configuration, and fully-spanned voids occurred in the lines above the vias for “via-below” configuration.On the other hand, failure analysis for CoWP-coated Cu structures showed that partiallyspanned voids below the via do not cause fatal failures in the downstream configuration. This is because the CoWP layer is conducting, and thus able to shunt current around the void. As a result, a large fully-spanning void is required to cause a failure, just like the upstream configuration. Thus the lifetime of an interconnect with a conducting cap layer is independent of whether the current is flowing upstream or downstream.


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