Relation between Defects on 4H-SiC Epitaxial Surface and Gate Oxide Reliability

2013 ◽  
Vol 740-742 ◽  
pp. 745-748 ◽  
Author(s):  
J. Sameshima ◽  
Osamu Ishiyama ◽  
Atsushi Shimozato ◽  
K. Tamura ◽  
H. Oshima ◽  
...  
Keyword(s):  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Wafer Surface ◽  
Cross Sectional ◽  
Mos Capacitors ◽  
Oxide Breakdown ◽  
Time Dependent Dielectric Breakdown ◽  
Oxide Reliability ◽  
Breakdown Region

Time-dependent dielectric breakdown (TDDB) measurement of MOS capacitors on an n-type 4 ° off-axis 4H-SiC(0001) wafer free from step-bunching showed specific breakdown in the Weibull distribution plots. By observing the as-grown SiC-epi wafer surface, two kinds of epitaxial surface defect, Trapezoid-shape and Bar-shape defects, were confirmed with confocal microscope. Charge to breakdown (Qbd) of MOS capacitors including an upstream line of these defects is almost the same value as that of a Wear-out breakdown region. On the other hand, the gate oxide breakdown of MOS capacitors occurred at a downstream line. It has revealed that specific part of these defects causes degradation of oxide reliability. Cross-sectional TEM images of MOS structure show that gate oxide thickness of MOS capacitor is non-uniform on the downstream line. Moreover, AFM observation of as-grown and oxidized SiC-epitaxial surfaces indicated that surface roughness of downstream line becomes 3-4 times larger than the as-grown one by oxidation process.

High Temperature Reliability Investigations up to 350 °C of Gate Oxide Capacitors realized in a Silicon-on-Insulator CMOS-Technology

2013 ◽  
Vol 2013 (HITEN) ◽  
pp. 000116-000121
Author(s):  
K. Grella ◽  
S. Dreiner ◽  
H. Vogt ◽  
U. Paschen
Keyword(s):  
High Temperature ◽  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Cmos Process ◽  
Oxide Breakdown ◽  
Time Dependent Dielectric Breakdown ◽  
Single Poly Eeprom

Standard Bulk-CMOS-technology targets use-temperatures of not more than 175 °C. With Silicon-on-Insulator-technologies (SOI), digital and analog circuitry is possible up to 250 °C and even more, but performance and reliability are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350 °C. The experiments were carried out on gate oxide capacitor structures which were realized in the Fraunhofer 1.0 μm SOI-CMOS process. This technology is based on 200 mm wafers and features, among others, three layers of tungsten metallization with excellent reliability concerning electromigration, voltage independent capacitors, high resistance resistors, and single-poly-EEPROM cells. The gate oxide thickness is 40 nm. Using the data of the TDDB-measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350 °C was evaluated. For a more detailed investigation, the current evolution in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250 °C, and make it possible to quickly evaluate the reliability of high temperature CMOS-technologies at use-temperature.

Reliability of 4H-SiC(000-1) MOS Gate Oxide Using N2O Nitridation

2009 ◽  
Vol 615-617 ◽  
pp. 557-560 ◽  
Author(s):  
Takuma Suzuki ◽  
Junji Senzaki ◽  
Tetsuo Hatakeyama ◽  
Kenji Fukuda ◽  
Takashi Shinohe ◽  
...  
Keyword(s):  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Band Offset ◽  
Mos Capacitors ◽  
Conduction Band Offset ◽  
Time Dependent Dielectric Breakdown ◽  
Oxide Reliability ◽  
Mos Gate

The oxide reliability of metal-oxide-semiconductor (MOS) capacitors on 4H-SiC(000-1) carbon face was investigated. The gate oxide was fabricated by using N2O nitridation. The effective conduction band offset (Ec) of MOS structure fabricated by N2O nitridation was increased to 2.2 eV compared with Ec = 1.7 eV for pyrogenic oxidation sample of. Furthermore, significant improvements in the oxide reliability were observed by time-dependent dielectric breakdown (TDDB) measurement. It is suggested that the N2O nitridation as a method of gate oxide fabrication satisfies oxide reliability on 4H-SiC(000-1) carbon face MOSFETs.

Reliability Investigations up to 350°C of Gate Oxide Capacitors Realized in a Silicon-on-Insulator CMOS Technology

2013 ◽  
Vol 10 (4) ◽  
pp. 150-154 ◽  
Author(s):  
K. Grella ◽  
S. Dreiner ◽  
H. Vogt ◽  
U. Paschen
Keyword(s):  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Cmos Process ◽  
Leakage Currents ◽  
Oxide Breakdown ◽  
Time Dependent Dielectric Breakdown ◽  
Operation Temperature

It is difficult to use standard bulk-CMOS-technology at temperatures higher than 175°C due to high pn-leakage currents. Silicon-on-insulator-technologies (SOI), on the other hand, are usable up to 250°C and even higher, because leakage currents can be reduced by two to three orders of magnitude. Nevertheless, performance and reliability of SOI devices are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350°C. The experiments were carried out on gate oxide capacitor structures realized in the Fraunhofer 1.0 μm SOI-CMOS process. The gate oxide thickness is 40 nm. Using the data of the TDDB measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350°C was evaluated. For a more detailed investigation, the evolution of the current in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250°C, and make it possible to quickly evaluate the reliability of high temperature CMOS technologies at operation temperature.

Evaluation of 4H-SiC Carbon Face Gate Oxide Reliability

2011 ◽  
Vol 679-680 ◽  
pp. 354-357
Author(s):  
Jody Fronheiser ◽  
Aveek Chatterjee ◽  
Ulrike Grossner ◽  
Kevin Matocha ◽  
Vinayak Tilak ◽  
...  
Keyword(s):  
Dielectric Breakdown ◽  
Inversion Layer ◽  
Gate Oxide ◽  
Dielectric Strength ◽  
Time To Failure ◽  
Research Groups ◽  
Mos Capacitors ◽  
Channel Mobility ◽  
Time Dependent Dielectric Breakdown ◽  
Oxide Reliability

The gate oxide reliability and channel mobility of carbon face (000-1) 4H Silicon Carbide (SiC) MOSFETs are investigated. Several gate oxidation processes including dry oxygen, pyrogenic steam, and nitrided oxides were investigated utilizing MOS capacitors for time dependent dielectric breakdown (TDDB), dielectric field strength, and MOSFETs for inversion layer mobility measurements. The results show the C-face can achieve reliability similar to the Si-face, however this is highly dependent on the gate oxide process. The reliability is inversely related to the field effect mobility where other research groups report that pyrogenic steam yields the highest electron mobility while this work shows it has weakest oxide in terms of dielectric strength and shortest time to failure.

Time Dependent Dielectric Breakdown in High Quality SiC MOS Capacitors

2016 ◽  
Vol 858 ◽  
pp. 615-618 ◽  
Author(s):  
Zakariae Chbili ◽  
Kin P. Cheung ◽  
Jason P. Campbell ◽  
Jaafar Chbili ◽  
Mhamed Lahbabi ◽  
...  
Keyword(s):  
Dielectric Breakdown ◽  
Oxide Thickness ◽  
Time Dependent ◽  
Production Environment ◽  
Early Failure ◽  
High Quality ◽  
Mos Capacitors ◽  
Time Dependent Dielectric Breakdown ◽  
Oxide Reliability

In this paper we report TDDB results on SiO2/SiC MOS capacitors fabricated in a matured production environment. A key feature is the absence of early failure out of over 600 capacitors tested. The observed field accelerations and activation energies are higher than what is reported on SiO2/Si of similar oxide thickness. The great improvement in oxide reliability and the deviation from typical SiO2/SiC observations are explained by the quality of the oxide in this study.

Gate Oxide Reliability of SiC MOSFETs and Capacitors Fabricated on 150mm Wafers

2019 ◽  
Vol 963 ◽  
pp. 745-748 ◽  
Author(s):  
Daniel J. Lichtenwalner ◽  
Shadi Sabri ◽  
Edward van Brunt ◽  
Brett Hull ◽  
Satyaki Ganguly ◽  
...  
Keyword(s):  
Activation Energy ◽  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Large Area ◽  
Temperature Dependent ◽  
Acceleration Parameter ◽  
Time Dependent Dielectric Breakdown ◽  
Oxide Reliability ◽  
Voltage Breakdown ◽  
Linear Field

Gate oxide reliability on silicon carbide MOSFETs and large-area SiC N-type capacitors was studied for devices fabricated on 150mm SiC substrates. Oxide lifetime was measured under accelerated stress conditions using constant-voltage time-dependent dielectric breakdown (TDDB) testing, or ramped-voltage breakdown (RBD) testing. TDDB results from 1200V Gen3 MOSFETs reveal a field acceleration parameter of about 35 nm/V, similar to values reported for SiO2 on silicon. Temperature-dependent RBD tests of large capacitors from 25°C to 200°C reveal an apparent activation energy of 0.24eV, indicating that oxide lifetime increases as the temperature is decreased, as expected. Using this acceleration parameter and activation energy in the linear field model, the gate oxide lifetime from MOSFET TDDB testing extrapolates to greater than 108 hours at a gate voltage of 15 VGS at 175°C.

Effect of Gate Wet Reoxidation on Reliability and Channel Mobility of Metal-Oxide-Semiconductor Field-Effect Transistors Fabricated on 4H-SiC(000-1)

2008 ◽  
Vol 600-603 ◽  
pp. 791-794 ◽  
Author(s):  
Takuma Suzuki ◽  
Junji Senzaki ◽  
Tetsuo Hatakeyama ◽  
Kenji Fukuda ◽  
Takashi Shinohe ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Field Effect ◽  
Dielectric Breakdown ◽  
Field Effect Transistors ◽  
Gate Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Channel Mobility ◽  
Time Dependent Dielectric Breakdown ◽  
Oxide Reliability

The channel mobility and oxide reliability of metal-oxide-semiconductor field-effect transistors (MOSFETs) on 4H-SiC (0001) carbon face were investigated. The gate oxide was fabricated by using dry-oxidized film followed by pyrogenic reoxidation annealing (ROA). Significant improvements in the oxide reliability were observed by time-dependent dielectric breakdown (TDDB) measurement. Furthermore, the field-effect inversion channel mobility (μFE) of MOSFETs fabricated by using pyrogenic ROA was as high as that of conventional 4H-SiC (0001) MOSFETs having the pyrogenic-oxidized gate oxide. It is suggested that the pyrogenic ROA of dry oxide as a method of gate oxide fabrication satisfies both channel mobility and oxide reliability on 4H-SiC (0001) carbon-face MOSFETs.

950 Volt 4H-SiC MOSFETs: DC and Transient Performance and Gate Oxide Reliability

2008 ◽  
Vol 600-603 ◽  
pp. 1131-1134 ◽  
Author(s):  
Kevin Matocha ◽  
Zachary Stum ◽  
Steve Arthur ◽  
Greg Dunne ◽  
Ljubisa Stevanovic
Keyword(s):  
Electric Field ◽  
Applied Electric Field ◽  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Time Dependent ◽  
Time To Failure ◽  
Time Dependent Dielectric Breakdown ◽  
Oxide Reliability ◽  
Blocking Voltage ◽  
Mean Time

SiC vertical MOSFETs were fabricated and characterized to achieve a blocking voltage of 950 Volts and a specific on-resistance of 8.4 mW-cm2. Extrapolations of time-dependent dielectric breakdown measurements versus applied electric field indicate that the gate oxide mean-time to failure is approximately 105 hours at 250°C.

Structure Of The Defects Responsible For B-Mode Breakdown Of Gate Oxide Grown On The Surface Of Silicon Wafers

1996 ◽  
Vol 442 ◽  
Author(s):  
T. Mera ◽  
J. Jablonski ◽  
M. Danbata ◽  
K. Nagai ◽  
M. Watanabe
Keyword(s):  
Gate Oxide ◽  
Wafer Surface ◽  
Cross Sectional ◽  
Oxide Breakdown ◽  
Breakdown Mechanism ◽  
Transmission Electron ◽  
Thermal Oxide ◽  
Before And After ◽  
Thick Oxide Layer ◽  
Unambiguous Detection

AbstractCrystal-originated pits are known as the defects responsible for B-mode Time Zero Dielectric Break-down (TZDB) of the gate oxide grown on the surface of Si wafers. In order to clarify the breakdown mechanism, we have analyzed the structure of those defects formed at the surface of bare and oxidized wafers. In the latter case the analysis has been done both before and after gate oxide breakdown. Electric breakdown has been accomplished by Cu decoration method, recognized as an effective tool for unambiguous detection and positioning of the defects causing B-mode TZDB. As revealed by cross-sectional transmission electron microscopy (XTEM), crystal-originated pits at the bare wafer surface are polyhedral pits having about 5-nm-thick oxide layer on the inner walls. During gate oxidation the thermal oxide is growing faster on the pit walls than on the wafer surface, except for the pit comers where the oxide thinning has been observed. Resulting concave comers of the oxidized pits are suggested to be the weak spots where B-mode TZDB occurs.

Characterization of 0.5 µm BiCMOS Gate Oxide Using Time Dependent Dielectric Breakdown Test

2010 ◽  
Vol 97-101 ◽  
pp. 40-44
Author(s):  
Mohd Zahrin A. Wahab ◽  
Azman Jalar ◽  
Shahrum Abdullah ◽  
Hazian Mamat
Keyword(s):  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Raw Material ◽  
Time Dependent ◽  
Process Equipment ◽  
Mos Capacitors ◽  
Time Dependent Dielectric Breakdown ◽  
Bicmos Technology ◽  
Set Up

This paper presents Time Dependent Dielectric Breakdown (TDDB) testing of gate oxide on 0.5µm BiCMOS Technology. The gate oxide quality for the technology has been investigated and furthermore to qualify the whole set up of the foundry from the process, equipment, cleanroom control and raw material used to produce high quality gate oxide and hence good quality of BiCMOS devices. TDDB test is the most widely used testing to check the quality of gate oxide and in this paper the TDDB test done on MOS capacitors fabricated using 0.5 µm BiCMOS Technology. Seven consecutive qualification lots have been tested and the data shown that TDDB measurement is capable to differentiate between accepted wafer and rejected wafer. The data also shown that TDDB test was capable to characterise 0.5 µm BiCMOS gate oxide with higher yield and comparable with reference lot from other foundry fab.

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