A Low Temperature Polycrystalline Si TFT Technology for Large area AMLCD Drivers

1997 ◽  
Vol 472 ◽  
Author(s):  
Krishna C. Saraswat ◽  
V. Subramanian ◽  
S. Jurichich
Keyword(s):  
Low Temperature ◽  
Silicon Germanium ◽  
Liquid Crystal Display ◽  
Amorphous Film ◽  
Economic Modeling ◽  
Film Deposition ◽  
Manufacturing Cost ◽  
Large Area ◽  
Device Structure ◽  
Glass Substrates

ABSTRACTIn this paper we describe a low thermal budget technology to fabricate high performance CMOS thin-film transistors (TFTs) in polycrystalline silicon and silicon/germanium on low cost glass substrates, for active-matrix liquid crystal display (AMLCD) applications. Based on modeling of delay times of the scan and data lines driven by n-channel TFTs we show that for AMLCDs with integrated drive circuits, mobility in excess of 40 cm2/V. sec will be required. Through proper optimization of amorphous film deposition, crystallization (nucleation and grain growth), fabrication process parameters and device structure we have obtained mobility in excess of 50 cm2/V. sec in Si TFTs, using conventional manufacturing technology compatible with glass substrates. Economic modeling suggests that low-temperature poly-TFT LCDs with integrated drivers will have a competitive manufacturing cost to LCDs of an equivalent size and resolution with α-Si pixel TFTs and single crystal drivers.

Low-temperature Growth of Poly-Si and SiGe Thin Films by Reactive Thermal CVD and Fabrication of High Mobility TFTs over 50 cm2/Vs

2003 ◽  
Vol 762 ◽  
Author(s):  
Jun-Ichi Hanna ◽  
Kousaku Shimizu
Keyword(s):  
Thin Films ◽  
Low Temperature ◽  
Silicon Germanium ◽  
Film Growth ◽  
Early Stage ◽  
Substrate Surface ◽  
Large Area ◽  
Glass Substrates ◽  
Thermal Cvd ◽  
Technical Requirements

AbstractWe have established a new thermal CVD technique, Reactive Thermal CVD, for polycrystalline silicon (poly-Si) and silicon germanium (poly-SiGe) thin films aiming at thin film transistors (TFTs) applications, in which a low substrate temperature of 450°C enables us to use glass substrates. This technique achieved high crystallinity at very early stage of the film growth, resulting no amorphous incubation layer on the substrate surface. We fabricated bottom and top gate n-and p-channel TFTs with these of 200 nm thick films on SiO2/Si wafers and glass substrates, respectively: the high field effect mobilities as high as 55 cm2/Vs and 25 cm2/Vs were achieved in the bottom-gate and top-gate TFTs, respectively. Here, we discuss the technical requirements in the low-temperature CVD technique for the large-area poly-Si thin films and how they can be achieved in the reactive thermal CVD.

Developing Monolithically Integrated CdTe Devices Deposited by AP-MOCVD

2013 ◽  
Vol 1538 ◽  
pp. 275-280
Author(s):  
S.L. Rugen-Hankey ◽  
V. Barrioz ◽  
A. J. Clayton ◽  
G. Kartopu ◽  
S.J.C. Irvine ◽  
...  
Keyword(s):  
Chemical Vapor ◽  
Thin Film Deposition ◽  
Deposition Process ◽  
Film Deposition ◽  
Aluminosilicate Glass ◽  
Organic Chemical ◽  
Large Area ◽  
Monolithically Integrated ◽  
Glass Substrates ◽  
Laser Scribing

ABSTRACTThin film deposition process and integrated scribing technologies are key to forming large area Cadmium Telluride (CdTe) modules. In this paper, baseline Cd1-xZnxS/CdTe solar cells were deposited by atmospheric-pressure metal organic chemical vapor deposition (AP-MOCVD) onto commercially available ITO coated boro-aluminosilicate glass substrates. Thermally evaporated gold contacts were compared with a screen printed stack of carbon/silver back contacts in order to move towards large area modules. P2 laser scribing parameters have been reported along with a comparison of mechanical and laser scribing process for the scribe lines, using a UV Nd:YAG laser at 355 nm and 532 nm fiber laser.

Multiscale structured low-temperature solid oxide fuel cells with 13 W power at 500 °C

2020 ◽  
Vol 13 (10) ◽  
pp. 3459-3468 ◽  
Author(s):  
Sung Soo Shin ◽  
Jeong Hun Kim ◽  
Kyung Taek Bae ◽  
Kang-Taek Lee ◽  
Sang Moon Kim ◽  
...  
Keyword(s):  
Thin Film ◽  
Fuel Cell ◽  
Low Temperature ◽  
Solid Oxide Fuel Cells ◽  
Thin Film Deposition ◽  
Film Deposition ◽  
Solid Oxide ◽  
Oxide Fuel ◽  
Large Area ◽  
Deposition Processes

A multiscale architectured solid oxide fuel cell is demonstrated by applying a large-area ceramic micropatterning and thin-film deposition processes.

Low-Temperature Polycrystalline Silicon Thin-Film Transistors for Large-Area Liquid Crystal Display

1992 ◽  
Vol 31 (Part 1, No. 12B) ◽  
pp. 4559-4562 ◽  
Author(s):  
Yutaka Miyata ◽  
Mamoru Furuta ◽  
Tatsuo Yoshioka ◽  
Tetsuya Kawamura
Keyword(s):  
Thin Film ◽  
Liquid Crystal ◽  
Low Temperature ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Liquid Crystal Display ◽  
Large Area ◽  
Silicon Thin Film

LARGE AREA GaN METAL SEMICONDUCTOR METAL (MSM) PHOTODIODE USING A THIN LOW TEMPERATURE GaN CAP LAYER

2008 ◽  
Vol 17 (01) ◽  
pp. 59-69 ◽  
Author(s):  
L. S. CHUAH ◽  
Z. HASSAN ◽  
H. ABU HASSAN ◽  
C. W. CHIN ◽  
S. M. THAHAB
Keyword(s):  
Low Temperature ◽  
Integrated Circuits ◽  
Dark Current ◽  
High Speed ◽  
Distributed Data ◽  
Large Area ◽  
Device Structure ◽  
Metal Semiconductor Metal ◽  
Large Active Area ◽  
Schottky Photodiode

Small area metal semiconductor metal (MSM) photodiode (PD) has been one of the most favoured detector choices for high speed optoelectronics integrated circuits due to their low parasitic capacitance and simple planar device structure, which is compatible with FETs. Large MSM PDs, on the other hand, can also be useful in many network and interconnect applications such as fibre distributed data interfaces. An MBE grown GaN metal semiconductor metal photodiode with a thin low temperature GaN (50nm) barrier enhancement layer is reported, which has low dark current. The detector using Nickel ( Ni ) Schottky metal fingers with 400 μm spacing on a large active area exhibit a low dark current of 1.23 mA at 10 V bias, which is about three orders of magnitude lower than that of the normal GaN Schottky photodiode.

Growth of Polycrystalline Silicon Films at Low Temperature by Plasma Enhanced Chemical Vapor Deposition

1995 ◽  
Vol 403 ◽  
Author(s):  
Y. Hatanaka ◽  
A. H. Jayatissa ◽  
K. Ishikawa ◽  
Y. Nakanishi
Keyword(s):  
Chemical Vapor Deposition ◽  
Low Temperature ◽  
Vapor Deposition ◽  
Polycrystalline Silicon ◽  
Liquid Crystal Display ◽  
Chemical Vapor ◽  
High Deposition Rate ◽  
Large Area ◽  
Wide Range ◽  
Si Films

AbstractPolycrystalline silicon (poly-Si) films are of great interest in the field of TFT fabrication for active matrix liquid crystal display(AM-LCD) applications. Low temperature depositions below 500 °C are necessary for using a glass substrate for the application to large area devices such as display devices. We investigated poly-Si growth at low temperature by plasma enhanced chemical vapor deposition (PECVD). Cathode deposition is used in which substrates are mounted on the powered electrode and a mesh electrode is attached on the cathode for protecting the growing surface from ion impacts. It is found that poly-Si films can be deposited in the wide range of SiH4 concentration even at 100%, and a high deposition rate of 35nm/min has been realized. This investigation gives highly promising results for poly-Si growth technology at low temperature.

scholarly journals Nanonet: Low-temperature-processed tellurium nanowire network for scalable p-type field-effect transistors and a highly sensitive phototransistor array

2021 ◽  
Vol 13 (1) ◽  
Author(s):  
Muhammad Naqi ◽  
Kyung Hwan Choi ◽  
Hocheon Yoo ◽  
Sudong Chae ◽  
Bum Jun Kim ◽  
...  
Keyword(s):  
Low Temperature ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Optical Measurements ◽  
Electrical Performance ◽  
Large Area ◽  
Nanowire Network ◽  
P Type ◽  
Nanowire Networks

AbstractLow-temperature-processed semiconductors are an emerging need for next-generation scalable electronics, and these semiconductors need to feature large-area fabrication, solution processability, high electrical performance, and wide spectral optical absorption properties. Although various strategies of low-temperature-processed n-type semiconductors have been achieved, the development of high-performance p-type semiconductors at low temperature is still limited. Here, we report a unique low-temperature-processed method to synthesize tellurium nanowire networks (Te-nanonets) over a scalable area for the fabrication of high-performance large-area p-type field-effect transistors (FETs) with uniform and stable electrical and optical properties. Maximum mobility of 4.7 cm2/Vs, an on/off current ratio of 1 × 104, and a maximum transconductance of 2.18 µS are achieved. To further demonstrate the applicability of the proposed semiconductor, the electrical performance of a Te-nanonet-based transistor array of 42 devices is also measured, revealing stable and uniform results. Finally, to broaden the applicability of p-type Te-nanonet-based FETs, optical measurements are demonstrated over a wide spectral range, revealing an exceptionally uniform optical performance.

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