Electrical Instabilities and 1/f Noise in Organic Pentacene Thin Film Transistors

2000 ◽  
Vol 660 ◽  
Author(s):  
P. V. Necliudov ◽  
M. Shur ◽  
D. J. Gundlach ◽  
T. N. Jackson
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Electrical Characteristics ◽  
Threshold Voltage Shift ◽  
Current Voltage ◽  
Noise Measurements ◽  
Current Voltage Characteristics ◽  
Amorphous Si ◽  
Bias Temperature Stress

ABSTRACTWe report on the influence of Bias-Temperature Stress (BTS) on the pentacene Thin Film Transistors (TFTs) electrical characteristics and on their 1/f noise level. The gate BTS primarily affects the TFT threshold voltage, leaving both mobility and sub-threshold slope values almost unchanged. The degree of the threshold voltage shift induced by the positive or negative BTS depends on the TFT design and the BTS parameters. The current-voltage characteristics time dependence of the organic TFTs, subjected to the BTS, resembles that for amorphous-Si TFTs. The results of the 1/f noise measurements in the organic TFTs allowed us to conclude that the gate BTS primarily affects the TFT contact regions, resulting in the increase of both the contact noise and the contact resistance.

scholarly journals Enhancement of Electrical Characteristics and Stability of Amorphous Si-Sn-O Thin Film Transistors with SiOx Passivation Layer

Materials ◽  
2018 ◽  
Vol 11 (8) ◽  
pp. 1440 ◽  
Author(s):  
Xianzhe Liu ◽  
Weijing Wu ◽  
Weifeng Chen ◽  
Honglong Ning ◽  
Xiaochen Zhang ◽  
...  
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Charge Trapping ◽  
Passivation Layer ◽  
Device Performance ◽  
Electrical Characteristics ◽  
Initial State ◽  
Large Size ◽  
Amorphous Si

In this research, a passivated methodology was proposed for achieving good electrical characteristics for back-channel-etch (BCE) typed amorphous Si-Sn-O thin film transistors (a-STO TFTs). This methodology implied that the thermal annealing (i.e., pre-annealing) should be carried out before deposition of a SiOx passivation layer. The pre-annealing played an important role in affecting device performance, which did get rid of the contamination of the lithography process. Simultaneously, the acceptor-like sub-gap density of states (DOS) of devices was extracted for further understanding the reason for improving device performance. It found that the SiOx layer could reduce DOS of the device and successfully protect the device from surroundings. Finally, a-STO TFT applied with this passivated methodology could possess good electrical properties including a saturation mobility of 4.2 ± 0.2 cm2/V s, a low threshold voltage of 0.00 V, a large on/off current ratio of 6.94 × 108, and a steep subthreshold swing of 0.23 V/decade. The threshold voltage slightly shifted under bias stresses and recovered itself to its initial state without any annealing procedure, which was attributed to the charge trapping in the bulk dielectric layers or interface. The results of this study indicate that a-STO TFT could be a robust candidate for realizing a large-size and high-resolution display.

scholarly journals Analysis of Threshold Voltage Shift for Full VGS/VDS/Oxygen-Content Span under Positive Bias Stress in Bottom-Gate Amorphous InGaZnO Thin-Film Transistors

Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 327
Author(s):  
Je-Hyuk Kim ◽  
Jun Tae Jang ◽  
Jong-Ho Bae ◽  
Sung-Jin Choi ◽  
Dong Myong Kim ◽  
...  
Keyword(s):  
Thin Film ◽  
Electric Field ◽  
Oxygen Content ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Electron Trapping ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Drain Side ◽  
Bottom Gate

In this study, we analyzed the threshold voltage shift characteristics of bottom-gate amorphous indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) under a wide range of positive stress voltages. We investigated four mechanisms: electron trapping at the gate insulator layer by a vertical electric field, electron trapping at the drain-side GI layer by hot-carrier injection, hole trapping at the source-side etch-stop layer by impact ionization, and donor-like state creation in the drain-side IGZO layer by a lateral electric field. To accurately analyze each mechanism, the local threshold voltages of the source and drain sides were measured by forward and reverse read-out. By using contour maps of the threshold voltage shift, we investigated which mechanism was dominant in various gate and drain stress voltage pairs. In addition, we investigated the effect of the oxygen content of the IGZO layer on the positive stress-induced threshold voltage shift. For oxygen-rich devices and oxygen-poor devices, the threshold voltage shift as well as the change in the density of states were analyzed.

Investigation on the Electrical Stability of 5,11-Bis(triethylsilylethynyl)anthradithiophene Thin-Film Transistors

2021 ◽  
Vol 21 (3) ◽  
pp. 1754-1760
Author(s):  
Joel Ndikumana ◽  
Jyothi Chintalapalli ◽  
Jin-Hyuk Kwon ◽  
Jin-Hyuk Bae ◽  
Jaehoon Park
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Ambient Air ◽  
Gate Insulator ◽  
Hydroxyl Groups ◽  
Electrical Stability ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Domain Boundaries

We investigate the effects of environmental conditions on the electrical stability of spin-coated 5,11-bis(triethylsilylethynyl)anthradithiophene (TES-ADT) thin-film transistors (TFTs) in which crosslinked poly(4-vinylphenol-co-methyl methacrylate) (PVP-co-PMMA) was utilized as a gate insulator layer. Atomic force microscopy observations show molecular terraces with domain boundaries in the spin-coated TEST-ADT semiconductor film. The TFT performance was observed to be superior in the ambient air condition. Under negative gate-bias stress, the TES-ADT TFTs showed a positive threshold voltage shift in ambient air and a negative threshold voltage shift under vacuum. These results are explained through a chemical reaction between water molecules in air and unsubstituted hydroxyl groups in the cross-linked PVP-co-PMMA as well as a charge-trapping phenomenon at the domain boundaries in the spin-coated TES-ADT semiconductor.

Origin of hysteresis in current-voltage characteristics of polycrystalline silicon thin-film transistors

2009 ◽  
Vol 105 (5) ◽  
pp. 054502 ◽  
Author(s):  
Horng-Chih Lin ◽  
Cheng-Hsiung Hung ◽  
Wei-Chen Chen ◽  
Zer-Ming Lin ◽  
Hsing-Hui Hsu ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Silicon Thin Film ◽  
Current Voltage ◽  
Current Voltage Characteristics

Threshold voltage shift under electrical stress in amorphous, polymorphous, and microcrystalline silicon bottom gate thin-film transistors

2009 ◽  
Vol 207 (5) ◽  
pp. 1245-1248 ◽  
Author(s):  
Maher Oudwan ◽  
Oumkelthoum Moustapha ◽  
Alexey Abramov ◽  
Dmitriy Daineka ◽  
Yvan Bonnassieux ◽  
...  
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Microcrystalline Silicon ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Electrical Stress ◽  
Bottom Gate
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