Planarization Issues in Wafer-Level Three-Dimensional (3D) Integration

2004 ◽  
Vol 816 ◽  
Author(s):  
J.-Q. Lu ◽  
G. Rajagopalan ◽  
M. Gupta ◽  
T.S. Cale ◽  
R.J. Gutmann
Keyword(s):  
Wafer Bonding ◽  
Three Dimensional ◽  
Silicon On Insulator ◽  
Wafer Level ◽  
3D Integration ◽  
Edge Chipping ◽  
3D Ics ◽  
Process Compatibility ◽  
Wafer Thinning ◽  
Thinning Process

AbstractMonolithic wafer-level three-dimensional (3D) ICs based upon bonding of processed wafers and die-to-wafer 3D ICs based upon bonding die to a host wafer require additional planarization considerations compared to conventional planar ICs and wafer-scale packaging. Various planarization issues are described, focusing on the more stringent technology requirements of monolithic wafer-level 3D ICs. The specific 3D IC technology approach considered here consists of wafer bonding with dielectric adhesives, a three-step thinning process of grinding, polishing and etching, and an inter-wafer interconnect process using copper damascene patterning. The use of a bonding adhesive to relax pre-bonding wafer planarization requirements is a key to process compatibility with standard IC processes. Minimizing edge chipping during wafer thinning requires understanding of the relationships between wafer bonding, thinning and pre-bonding IC processes. The advantage of silicon-on-insulator technology in alleviating planarization issues with wafer thinning for 3D ICs is described.

Wafer Thinning for Monolithic 3D Integration

2003 ◽  
Vol 766 ◽  
Author(s):  
A. Jindal ◽  
J.Q. Lu ◽  
Y. Kwon ◽  
G. Rajagopalan ◽  
J.J. McMahon ◽  
...  
Keyword(s):  
3D Integration ◽  
Edge Chipping ◽  
Si Substrates ◽  
Interconnect Test ◽  
Etch Stop ◽  
Etch Stop Layer ◽  
Multi Level ◽  
Process Uniformity ◽  
Wafer Thinning ◽  
Thinning Process

AbstractA three-step baseline process for thinning of bonded wafers for applications in threedimensional (3D) integration is presented. The Si substrate of top bonded wafer is uniformly thinned to ~35 μm by backside grinding and polishing, followed by wet-etching using TMAH. No visible changes at the bonding interface and damage-free interconnect structures are observed after the thinning process. Both mechanical and electrical integrity of the bonded pairs are maintained after the three-step baseline thinning process, with electrical tests on wafers with multi-level copper interconnect test structures showing only a slight change after bonding and thinning. This thinning process works well for Si removal to an etch-stop layer, although present process uniformity is not adequate to thin bulk Si substrates. Other issues such as wafer breakage and edge chipping during Si thinning and their possible solutions are also addressed.

Dielectric GlueWafer Bonding For 3D ICs

2003 ◽  
Vol 766 ◽  
Author(s):  
Y. Kwon ◽  
A. Jinda ◽  
J.J. McMahon ◽  
J.Q. Lu ◽  
R.J. Gutmann ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Bonding Strength ◽  
Three Dimensional ◽  
Wafer Level ◽  
Four Point Bending ◽  
Mechanical And Electrical Properties ◽  
3D Ics ◽  
Bond Interface ◽  
Three Dimensional Integrated Circuit ◽  
Wafer Thinning

AbstractA process to bond 200 mm wafers for wafer-level three-dimensional integrated circuit (3D-IC) applications is discussed. Four-point bending is used to quantify the bonding strength and identify the weak interface. Using benzocylcobutene (BCB) glue, the bonding strength depends on (1) glue thickness, (2) glue film preparation, and (3) materials and structures on the wafer(s). A seamless BCB-to-BCB bond interface provides the highest bonding strength compared to other interfaces in these structures (> 34 J/m2). Mechanical and electrical properties of a wafer with copper interconnect structures are preserved after wafer bonding and wafer thinning, confirming the potential of the bonding process for 3D ICs.

Three Dimensional Integration with Benzocyclobutene as the Wafer-Bonding Medium

2004 ◽  
Vol 833 ◽  
Author(s):  
Sang Kevin Kim ◽  
Lei Xue ◽  
Sandip Tiwari
Keyword(s):  
Integrated Circuits ◽  
Wafer Bonding ◽  
Three Dimensional ◽  
Experimental Results ◽  
Device Layer ◽  
3D Integration ◽  
Wafer Scale ◽  
3D Ics ◽  
Fabrication Procedure ◽  
3D Fabrication

ABSTRACTA successful wafer-scale device layering process for fabricating three-dimensional integrated circuits (3D ICs) using Benzocyclobutene (BCB) is described. In the reported embodiment of the method, a sub-micron thick “donor” device layer is transplanted onto a fully fabricated “host” wafer with BCB as the intervening medium. Experimental results, including RIE study and planarization of BCB processed through the 3D fabrication procedure are reported. We conclude with an approach to alleviate BCB and fabrication induced wafer bowing, which leads to poor wafer to wafer alignment in 3D integration.

Global Planarization Requirements for Wafer-Level Three-Dimensional (3D) ICs

2005 ◽  
Author(s):  
R. J. Gutmann ◽  
J. J. McMahon ◽  
J.-Q. Lu
Keyword(s):  
Integrated Circuit ◽  
Thermal Processing ◽  
Three Dimensional ◽  
Wafer Level ◽  
3D Integration ◽  
3D Ics ◽  
Technology Platforms ◽  
Technology Focus ◽  
Feature Scale ◽  
Ic Technology

Planarization needs for integrated circuit (IC) technology focus on feature-scale (100nm–1μm) and die-scale (5mm-20mm) dimensions. As three-dimensional (3D) integration moves from die-by-die assembly to wafer-level integration to provide a higher density of low electrical parasitic vertical interconnects (or vias), wafer-level planarization needs to be considered. Planarization needs depend upon the 3D technology platform approach (such as (1) blanket bonding followed by inter-wafer interconnect processing or via-first processing followed by bonding and thinning to expose the vias and (2) the number of wafers in a 3D stack) and the processing conditions used in fabricating the wafers to be 3D integrated (in particular, the built-in stress levels and post-bonding thermal processing budget). This invited presentation includes a summary of the current interest in wafer-level 3D integration in both the academic and industrial research community. Wafer-level planarization issues with different technology platforms are presented, and the limited results presented in the literature to date are summarized. The importance of wafer-level planarization compared to bonding, thinning and wafer-to-wafer alignment is discussed.

Fundamental Limits for 3D Wafer-to-Wafer Alignment Accuracy

2004 ◽  
Vol 812 ◽  
Author(s):  
M. Wimplinger ◽  
J.-Q. Lu ◽  
J. Yu ◽  
Y. Kwon ◽  
T. Matthias ◽  
...  
Keyword(s):  
Three Dimensional ◽  
Alignment Accuracy ◽  
Wafer Level ◽  
3D Integration ◽  
3D Technology ◽  
Fundamental Limits ◽  
Technology Platforms ◽  
Global Interconnects ◽  
Wafer Thinning ◽  
Alternative Alignment

AbstractWafer-level three-dimensional (3D) integration as an emerging architecture for future chips offers high interconnect performance by reducing delays of global interconnects and high functionality with heterogeneous integration of materials, devices, and signals. Various 3D technology platforms have been investigated, with different combinations of alternative alignment, bonding, thinning and inter-wafer interconnection technologies. Precise alignment on the wafer level is one of the key challenges affecting the performance of the 3D interconnects. After a brief overview of the wafer-level 3D technology platforms, this paper focuses on waferto-wafer alignment fundamentals. Various alignment methods are reviewed. A higher emphasis lies on the analysis of the alignment accuracy. In addition to the alignment accuracy achieved prior to bonding, the impacts of wafer bonding and subsequent wafer thinning will be discussed.

High Precision Low Temperature Direct Wafer Bonding Technology for Wafer-Level 3D ICs Manufacturing

2016 ◽  
Vol 75 (9) ◽  
pp. 345-353 ◽  
Author(s):  
F. Kurz ◽  
T. Plach ◽  
J. Suss ◽  
T. Wagenleitner ◽  
D. Zinner ◽  
...  
Keyword(s):  
Low Temperature ◽  
High Precision ◽  
Wafer Bonding ◽  
Wafer Level ◽  
3D Ics ◽  
Direct Wafer Bonding ◽  
Bonding Technology

200. mm Silicon Wafer-to-Wafer Bonding with Thin Ti Layer under BEOL-Compatible Process Conditions

2004 ◽  
Vol 843 ◽  
Author(s):  
J. Yu ◽  
J. J. McMahon ◽  
J.-Q. Lu ◽  
R. J. Gutmann
Keyword(s):  
Wafer Bonding ◽  
Three Dimensional ◽  
Complete Removal ◽  
External Pressure ◽  
Reduced Form ◽  
Process Conditions ◽  
Manufacturing Cost ◽  
Wafer Level ◽  
Integrity Test ◽  
Wafer Pair

ABSTRACTWafer level monolithic three-dimensional (3D) integration is an emerging technology to realize enhanced performance and functionality with reduced form-factor and manufacturing cost. The cornerstone for this 3D processing technology is full-wafer bonding under back-end-of-the-line (BEOL) compatible process conditions. For the first time to our knowledge, we demonstrate nearly void-free 200 mm wafer-to-wafer bonding with an ultra-thin Ti adhesive coating, annealed at BEOL-compatible temperature (400 °C) in vacuum with external pressure applied. Mechanical integrity test showed that bonded wafer pair survived after a stringent three-step thinning process (grinding/polishing/wet-etching) with complete removal of top Si wafer, while allowing optical inspection of bonding interface. Mechanisms contributing to the strong bonding at Ti/Si interface are briefly discussed.

Patterned wafers backside thinning for 3-D Integration and multilayer stack achievement by direct wafer bonding

2008 ◽  
Vol 1079 ◽  
Author(s):  
Barbara Charlet ◽  
Antoine Chiteboun ◽  
Marc Zussy ◽  
Laurent Bally ◽  
Patrick Leduc ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
3D Structure ◽  
Wafer Level ◽  
3D Integration ◽  
Patterned Substrate ◽  
Patterned Wafers ◽  
Direct Wafer Bonding ◽  
Scaling Down ◽  
Silicon Thickness ◽  
Wafer Thinning

ABSTRACTScaling down the devices to keep increasing the integrated circuits (ICs) performance at the rate defined by Moore's [1] law becomes more and more difficult and so costly that new circuits architectures and new integration technologies are investigated. One of the most promising ways in integration technology is the vertical stacking of circuits, also called “3D Integration”. One of the challenges in this technology is the patterned substrate backside thinning. Compatibility with the whole 3D Integration process has to be guaranteed, the existing circuit has to be kept intact and the bonding interface mustn't be damaged. In this study we discuss some experimental results of wafer thinning by grinding and polishing of molecular bonded silicon wafers applied to 3D Integration [2-4]. The wafer with patterned copper interconnections are stacked by direct SiO2 bonding and thinned down on one backside. These stacks are then bonded again to one or two circuits via a deposited oxide on the thinned surface. The top bulk Si surface was thinned down again on one backside, giving a multi layers stack. This wafer level vertical assembly demonstrates the possibility to adjust the remaining Silicon thickness to small values (<15μm) and then bond the thinned surface to achieve multiple layer 3D structure.

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