Global Planarization Requirements for Wafer-Level Three-Dimensional (3D) ICs

2005 ◽  
Author(s):  
R. J. Gutmann ◽  
J. J. McMahon ◽  
J.-Q. Lu
Keyword(s):  
Integrated Circuit ◽  
Thermal Processing ◽  
Three Dimensional ◽  
Wafer Level ◽  
3D Integration ◽  
3D Ics ◽  
Technology Platforms ◽  
Technology Focus ◽  
Feature Scale ◽  
Ic Technology

Planarization needs for integrated circuit (IC) technology focus on feature-scale (100nm–1μm) and die-scale (5mm-20mm) dimensions. As three-dimensional (3D) integration moves from die-by-die assembly to wafer-level integration to provide a higher density of low electrical parasitic vertical interconnects (or vias), wafer-level planarization needs to be considered. Planarization needs depend upon the 3D technology platform approach (such as (1) blanket bonding followed by inter-wafer interconnect processing or via-first processing followed by bonding and thinning to expose the vias and (2) the number of wafers in a 3D stack) and the processing conditions used in fabricating the wafers to be 3D integrated (in particular, the built-in stress levels and post-bonding thermal processing budget). This invited presentation includes a summary of the current interest in wafer-level 3D integration in both the academic and industrial research community. Wafer-level planarization issues with different technology platforms are presented, and the limited results presented in the literature to date are summarized. The importance of wafer-level planarization compared to bonding, thinning and wafer-to-wafer alignment is discussed.

Planarization Issues in Wafer-Level Three-Dimensional (3D) Integration

2004 ◽  
Vol 816 ◽  
Author(s):  
J.-Q. Lu ◽  
G. Rajagopalan ◽  
M. Gupta ◽  
T.S. Cale ◽  
R.J. Gutmann
Keyword(s):  
Wafer Bonding ◽  
Three Dimensional ◽  
Silicon On Insulator ◽  
Wafer Level ◽  
3D Integration ◽  
Edge Chipping ◽  
3D Ics ◽  
Process Compatibility ◽  
Wafer Thinning ◽  
Thinning Process

AbstractMonolithic wafer-level three-dimensional (3D) ICs based upon bonding of processed wafers and die-to-wafer 3D ICs based upon bonding die to a host wafer require additional planarization considerations compared to conventional planar ICs and wafer-scale packaging. Various planarization issues are described, focusing on the more stringent technology requirements of monolithic wafer-level 3D ICs. The specific 3D IC technology approach considered here consists of wafer bonding with dielectric adhesives, a three-step thinning process of grinding, polishing and etching, and an inter-wafer interconnect process using copper damascene patterning. The use of a bonding adhesive to relax pre-bonding wafer planarization requirements is a key to process compatibility with standard IC processes. Minimizing edge chipping during wafer thinning requires understanding of the relationships between wafer bonding, thinning and pre-bonding IC processes. The advantage of silicon-on-insulator technology in alleviating planarization issues with wafer thinning for 3D ICs is described.

Dielectric GlueWafer Bonding For 3D ICs

2003 ◽  
Vol 766 ◽  
Author(s):  
Y. Kwon ◽  
A. Jinda ◽  
J.J. McMahon ◽  
J.Q. Lu ◽  
R.J. Gutmann ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Bonding Strength ◽  
Three Dimensional ◽  
Wafer Level ◽  
Four Point Bending ◽  
Mechanical And Electrical Properties ◽  
3D Ics ◽  
Bond Interface ◽  
Three Dimensional Integrated Circuit ◽  
Wafer Thinning

AbstractA process to bond 200 mm wafers for wafer-level three-dimensional integrated circuit (3D-IC) applications is discussed. Four-point bending is used to quantify the bonding strength and identify the weak interface. Using benzocylcobutene (BCB) glue, the bonding strength depends on (1) glue thickness, (2) glue film preparation, and (3) materials and structures on the wafer(s). A seamless BCB-to-BCB bond interface provides the highest bonding strength compared to other interfaces in these structures (> 34 J/m2). Mechanical and electrical properties of a wafer with copper interconnect structures are preserved after wafer bonding and wafer thinning, confirming the potential of the bonding process for 3D ICs.

Fundamental Limits for 3D Wafer-to-Wafer Alignment Accuracy

2004 ◽  
Vol 812 ◽  
Author(s):  
M. Wimplinger ◽  
J.-Q. Lu ◽  
J. Yu ◽  
Y. Kwon ◽  
T. Matthias ◽  
...  
Keyword(s):  
Three Dimensional ◽  
Alignment Accuracy ◽  
Wafer Level ◽  
3D Integration ◽  
3D Technology ◽  
Fundamental Limits ◽  
Technology Platforms ◽  
Global Interconnects ◽  
Wafer Thinning ◽  
Alternative Alignment

AbstractWafer-level three-dimensional (3D) integration as an emerging architecture for future chips offers high interconnect performance by reducing delays of global interconnects and high functionality with heterogeneous integration of materials, devices, and signals. Various 3D technology platforms have been investigated, with different combinations of alternative alignment, bonding, thinning and inter-wafer interconnection technologies. Precise alignment on the wafer level is one of the key challenges affecting the performance of the 3D interconnects. After a brief overview of the wafer-level 3D technology platforms, this paper focuses on waferto-wafer alignment fundamentals. Various alignment methods are reviewed. A higher emphasis lies on the analysis of the alignment accuracy. In addition to the alignment accuracy achieved prior to bonding, the impacts of wafer bonding and subsequent wafer thinning will be discussed.

Fast Thermal Analysis of Vertically Integrated Circuits (3-D ICs) Using Power Blurring Method

2009 ◽  
Author(s):  
Je-Hyoung Park ◽  
Ali Shakouri ◽  
Sung-Mo Kang
Keyword(s):  
Integrated Circuits ◽  
Power Dissipation ◽  
Three Dimensional ◽  
Computation Time ◽  
Maximum Error ◽  
3D Ic ◽  
Additional Advantage ◽  
3D Ics ◽  
Ic Technology ◽  
Power Blurring

CMOS VLSI technology has been facing various technical challenges as the feature sizes scale down. To overcome the challenges imposed by the shrink of the conventional on-chip interconnect system in IC chips, alternative interconnect technologies are being developed: one of them is three dimensional chips (3D ICs). Even though 3D IC technology is a promising solution for interconnect bottlenecks, thermal issues can be exacerbated. Thermal-aware design and optimization will be more critical in 3D IC technology than conventional planar IC technology, and hence accurate temperature profiles of each active layer will become very important. In 3D ICs, temperature profile of one layer depends not only on its own power dissipation but also on the heat transferred from other layers. Thus, thermal considerations for 3D ICs need to be done in a holistic manner even if each layer can be designed and fabricated individually. Conventional grid-based temperature computation methods are accurate but are computationally expensive, especially for 3D ICs. To increase computational efficiency, we developed a matrix convolution technique, called Power Blurring (PB) for 3D ICs. The temperature resulting from any arbitrary power dissipation in each layer of the 3D chip can be computed quickly. The PB method has been validated against commercial FEA software, ANSYS. Our method yields good results with maximum error less than 2% for various case studies and reduces the computation time by a factor of ∼ 60. The additional advantage is the possibility to evaluate different power dissipation profiles without the need to re-mesh the whole 3D chip structure.

Reliable Design of TSV in Free-Standing Wafers and 3D Integrated Packages

2011 ◽  
Author(s):  
Xi Liu ◽  
Margaret Simmons-Matthews ◽  
Kurt P. Wachtler ◽  
Suresh K. Sitaraman
Keyword(s):  
Integrated Circuit ◽  
Mechanical Performance ◽  
Semiconductor Industry ◽  
Three Dimensional ◽  
Wafer Level ◽  
Free Standing ◽  
Design Factor ◽  
Reliable Design ◽  
Reliability Issue ◽  
Key Enabling Technologies

Through-silicon via (TSV), being one of the key enabling technologies for three dimensional (3D) Integrated Circuit (IC) stacking, silicon interposer technology, and advanced wafer level packaging (WLP), has attracted tremendous interest throughout the semiconductor industry. However, limited work addresses TSV reliability issue, and most of the existing reliability studies focus on the thermo-mechanical performance of TSVs in a free-standing wafer, rather than in an integrated package. In this paper, three-dimensional thermomechanical Finite-Element (FE) models with TSVs in both free-standing wafers and 3D integrated packages have been built and analyzed. In addition, Design of Experiments (DOE) based approach has been used to understand the effect of various parameters. Results show that the selection of underfill materials between stacked dies is the most dominating design factor for TSV/microbump reliability.

scholarly journals Wafer-Level 3D Integration Based on Poly (Diallyl Phthalate) Adhesive Bonding

Micromachines ◽  
2021 ◽  
Vol 12 (12) ◽  
pp. 1586
Author(s):  
Zhong Fang ◽  
Peng You ◽  
Yijie Jia ◽  
Xuchao Pan ◽  
Yunlei Shi ◽  
...  
Keyword(s):  
Adhesive Bonding ◽  
Low Cost ◽  
Three Dimensional ◽  
System Level ◽  
Process Conditions ◽  
Wafer Level ◽  
3D Integration ◽  
Bonding Pressure ◽  
Curing Conditions ◽  
Integration Technology

Three-dimensional integration technology provides a promising total solution that can be used to achieve system-level integration with high function density and low cost. In this study, a wafer-level 3D integration technology using PDAP as an intermediate bonding polymer was applied effectively for integration with an SOI wafer and dummy a CMOS wafer. The influences of the procedure parameters on the adhesive bonding effects were determined by Si–Glass adhesive bonding tests. It was found that the bonding pressure, pre-curing conditions, spin coating conditions, and cleanliness have a significant influence on the bonding results. The optimal procedure parameters for PDAP adhesive bonding were obtained through analysis and comparison. The 3D integration tests were conducted according to these optimal parameters. In the tests, process optimization was focused on Si handle-layer etching, PDAP layer etching, and Au pillar electroplating. After that, the optimal process conditions for the 3D integration process were achieved. The 3D integration applications of the micro-bolometer array and the micro-bridge resistor array were presented. It was confirmed that 3D integration based on PDAP adhesive bonding is suitable for the fabrication of system-on-chip when using MEMS and IC integration and that it is especially useful for the fabrication of low-cost suspended-microstructure on-CMOS-chip systems.

Overview and Outlook of Three-Dimensional Integrated Circuit Packaging, Three-Dimensional Si Integration, and Three-Dimensional Integrated Circuit Integration

2014 ◽  
Vol 136 (4) ◽  
Author(s):  
John H. Lau
Keyword(s):  
Integrated Circuit ◽  
State Of The Art ◽  
Three Dimensional ◽  
High Volume ◽  
3D Integration ◽  
3D Ic ◽  
3D Ic Packaging ◽  
Ic Packaging ◽  
Circuit Integration ◽  
Three Dimensional Integrated Circuit

3D integration consists of 3D integrated circuit (IC) packaging, 3D Si integration, and 3D IC integration. They are different and in general the through-silicon via (TSV) separates 3D IC packaging from 3D Si/IC integrations since the latter two use TSV but 3D IC packaging does not. 3D Si integration and 3D IC integration are different. 3D IC integration stacks up the thin chips with TSV and microbump, while 3D Si integration stacks up thin wafers with TSV alone (i.e., bumpless). TSV is the heart of 3D Si/IC integrations and is the focus of this investigation. Also, the state-of-the-art, challenge, and trend of 3D integration will be presented and examined. Furthermore, supply chain readiness for high volume manufacturing (HVM) of TSVs is discussed.

A Micro-channel Cooling Model For a Three-dimensional Integrated Circuit Considering Through-silicon Vias

2020 ◽  
Vol 12 ◽  
Author(s):  
Kang-Jia Wang ◽  
Hong-Chang Sun ◽  
Kui-Zhi Wang
Keyword(s):  
Integrated Circuit ◽  
Heat Dissipation ◽  
Three Dimensional ◽  
Micro Channel ◽  
3D Ic ◽  
Through Silicon Vias ◽  
3D Ics ◽  
Three Dimensional Integrated Circuit ◽  
Silicon Vias ◽  
Cooling Model

Background: With the increase of the integration degree of the three-dimensional integrated circuit(3D IC), the thermal power consumption per unit volume increases greatly, which makes the chip temperature rise. High temperature could affect the performance of the devices and even lead to thermal failure. So, the thermal management for 3D ICs is becoming a major concern. Objective: The aim of the research is to establish a micro-channel cooling model for a three-dimensional integrated circuit(3D IC) considering the through-silicon vias(TSVs). Methods: By studying the structure of the TSVs, the equivalent thermal resistance of each layer is formulated. Then the one-dimensional micro-channel cooling thermal analytical model considering the TSVs was proposed and solved by the existing sparse solvers such as KLU. Results: The results obtained in this paper reveal that the TSVs can effectively improve the heat dissipation, and its maximal temperature reduction is about 10.75%. The theoretical analysis is helpful to optimize the micro-channel cooling system for 3D ICs. Conclusion: The TSV has an important influence on the heat dissipation of 3D IC, which can improve its heat dissipation characteristic

Three Dimensional Integration with Benzocyclobutene as the Wafer-Bonding Medium

2004 ◽  
Vol 833 ◽  
Author(s):  
Sang Kevin Kim ◽  
Lei Xue ◽  
Sandip Tiwari
Keyword(s):  
Integrated Circuits ◽  
Wafer Bonding ◽  
Three Dimensional ◽  
Experimental Results ◽  
Device Layer ◽  
3D Integration ◽  
Wafer Scale ◽  
3D Ics ◽  
Fabrication Procedure ◽  
3D Fabrication

ABSTRACTA successful wafer-scale device layering process for fabricating three-dimensional integrated circuits (3D ICs) using Benzocyclobutene (BCB) is described. In the reported embodiment of the method, a sub-micron thick “donor” device layer is transplanted onto a fully fabricated “host” wafer with BCB as the intervening medium. Experimental results, including RIE study and planarization of BCB processed through the 3D fabrication procedure are reported. We conclude with an approach to alleviate BCB and fabrication induced wafer bowing, which leads to poor wafer to wafer alignment in 3D integration.

scholarly journals A Behavioral DC Model of 3D Distributed Diodes in Presence of Wideband Microwaves on Active Substrate Boards

2020 ◽  
Author(s):  
Pragnan Chakravorty
Keyword(s):  
Integrated Circuit ◽  
Printed Circuit Board ◽  
Three Dimensional ◽  
Circuit Board ◽  
Actual Behavior ◽  
Rf Components ◽  
Active Substrate ◽  
New Type ◽  
Dc Bias ◽  
Ic Technology

In the past few years, a new type of circuit board, named here as active substrate board (ASB), was introduced over circuit applications of diodes. Unlike a traditional printed circuit board (PCB), an ASB has its substrate made of a semiconductor. The inability of the traditional integrated circuit (IC) technology to integrate wavelength dependent radio frequency (RF) components triggered the advent of ASBs. These boards draw desirable features from IC as well as PCB technologies. Unprecedented challenges came up in modeling the different devices fabricated on an ASB owing to their large sizes and the presence of wideband microwaves. So far, modeling the effect of large sizes and ambient microwaves on DC bias of diodes have not been considered in scientific literature. Furthermore, the state of the art numerical simulators are unable to imitate the behavior of such diodes observed over measurements. Here, a semi-analytical, behavioral DC model of three dimensional (3D), distributed diodes on ASB is presented that is fairly accurate in predicting the actual behavior of the diodes. The model also opines a novel phenomenon of an AC affecting a DC with an added resistance.

Sign in / Sign up

Export Citation Format

Share Document