Low Temperature PECVD Silicon Oxide For Devices And Circuits On Flexible Substrates

2003 ◽  
Vol 769 ◽  
Author(s):  
Mark Meitine ◽  
Andrei Sazonov
Keyword(s):  
Low Temperature ◽  
Electronic Properties ◽  
Silicon Oxide ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Mos Capacitors ◽  
Plastic Substrates ◽  
Temperature Oxide ◽  
Stress Uniformity ◽  
Deposited Films

AbstractThe aim of this research is to develop low temperature gate dielectric/passivation layer for μc-Si and poly-Si based devices and circuits compatible with plastic substrates.The PECVD silicon oxide films were fabricated from mixture of silane and nitrous oxide at 250 °C, 120 °C and 75 °C. Helium, argon and nitrogen were used as diluent gases to optimize density, stress, uniformity, and electronic properties.Chemical composition and bonding in the films were studied by FTIR spectroscopy. The absorption peak at 1075-1080 cm-1 observed in the spectrum of each film corresponds to SiO2 stretching mode. No presence of SiH stretching or NH-stretching vibrations was found in the FTIR spectra of the samples.Film uniformity was varied from 1.44 % to 5.60 % for 3“×3” area. Four wafers were processed at the same time. The deposited films have compressive stress varied from 0.063 GPa to 0.117 GPa. Respective film density is in the range from 1.63 g/cm3 to 1.77 g/cm3.The electronic properties were studied on MOS capacitors with 200 nm thick SiOx. The dielectric permittivity was in the range between 2.03 and 3.57. The dielectric breakdown at 9 MV/cm was observed for the films deposited at 120 °C. The films deposited at higher temperatures are characterized by lower leakage current density, which was 3.7.10-10 A/cm2 for the sample deposited at 250 °C, 9.10-9 A/cm2 for 120 °C, and 2.2.10-8 A/cm2 for 75 °C at 5 MV/cm.The a-Si:H based TFTs were fabricated using low temperature oxide as gate dielectric. TFTs demonstrate threshold voltage (3.02 – 4.12 V) and mobility (0.12 – 0.59 cm2/Vs) comparing with those using silicon nitride.

Analysis of C-Face 4H-SiC MOS Capacitors with ZrO2 Gate Dielectric

2014 ◽  
Vol 778-780 ◽  
pp. 635-638 ◽  
Author(s):  
Le Shan Chan ◽  
Yu Hao Chang ◽  
Kung Yen Lee
Keyword(s):  
High Frequency ◽  
Room Temperature ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Annealing Process ◽  
Rapid Thermal Annealing Process ◽  
Leakage Currents ◽  
Mos Capacitors ◽  
Thermal Annealing Process ◽  
The Difference

ZrO2 films were deposited on C-face 4H-SiC substrates by using an RF sputter at a temperature of 200°C. Then, ZrO2 films were treated with RTA (rapid thermal annealing) process in Argon (Ar) ambient at 600°C, 700°C and 800°C for 4 minutes, respectively. The samples with RTA process show the lower leakage currents. As the measure temperature increases from room temperature (RT) to 150°C, the dielectric breakdown voltage reduces from 3 V to 1 V. The difference between quasi C-V characteristics and high frequency C-V characteristics at 1 MHz becomes larger with increasing RTA temperature. The C-V curves also shift to the left side as the measure temperature increases from RT to 150°C. It also shows the ledge on the C-V curves of samples with RTA at elevated measure temperature.

Electrical Characteristics of TaOxNy/ZrSixOy Stack Gate Dielectric for MOS Device Applications

2001 ◽  
Vol 670 ◽  
Author(s):  
Hyungsuk Jung ◽  
Hyundoek Yang ◽  
Kiju Im ◽  
Hyunsang Hwang
Keyword(s):  
Interfacial Layer ◽  
Silicon Oxide ◽  
Gate Dielectric ◽  
Oxide Thickness ◽  
Tem Analysis ◽  
Mos Capacitors ◽  
Zirconium Silicate ◽  
Transmission Electron ◽  
High K ◽  
Device Applications

ABSTRACTThis letter describes a unique process for the preparation of high quality tantalum oxynitride (TaOxNy) with zirconium silicate (ZrSixOy) as an interfacial layer for use in gate dielectric applications. Compared with conventional native silicon oxide and oxynitride as an interfacial layer, tantalum oxynitride (TaOxNy) MOS capacitors using zirconium silicate (ZrSixOy) as an interfacial layer exhibit lower leakage current levels at the same equivalent oxide thickness. We were able to confirm TaOxNy/ZrSixOy stack structure by auger electron spectroscopy (AES) and transmission electron microscope (TEM) analysis. The estimated dielectric constant of TaOxNy and ZrSixOywere approximately 67 and 7, respectively. The zirconium silicate is a promising interfacial layer for future high-k gate dielectric applications.

A solution-processed silicon oxide gate dielectric prepared at a low temperature via ultraviolet irradiation for metal oxide transistors

2016 ◽  
Vol 4 (44) ◽  
pp. 10486-10493 ◽  
Author(s):  
Hyeon Joo Seul ◽  
Hyun-Gwan Kim ◽  
Man-Young Park ◽  
Jae Kyeong Jeong
Keyword(s):  
Low Temperature ◽  
Metal Oxide ◽  
Ultraviolet Irradiation ◽  
Silicon Oxide ◽  
Gate Dielectric ◽  
Solution Processed ◽  
Facile Route

A facile route for the preparation of a solution-processed silicon oxide dielectric from perhydropolysilazane (PHPS) at a low temperature (≤150 °C) is proposed.

Low-temperature processable inherently photosensitive polyimide gate dielectric for organic thin-film transistors: Synthesis, characterization, and application to transistors

2005 ◽  
Vol 20 (4) ◽  
pp. 931-939 ◽  
Author(s):  
Seungmoon Pyo ◽  
Hyunsam Son ◽  
Mi Hye Yi
Keyword(s):  
Thin Film ◽  
Low Temperature ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Low Cost ◽  
Polyimide Film ◽  
Organic Thin Film Transistors ◽  
Organic Thin Film ◽  
Aromatic Diamines ◽  
Plastic Substrates

Low-temperature processable inherently photosensitive polyimide was prepared from a dianhydride, 3,3′,4,4′-benzophenone tetracarboxylic dianhydride, and aromatic diamines, 4,4′-diamino-3,3′dimethyl-diphenylmethane, through a polycondensation reaction, followed by a chemical imidization method. The photosensitive polyimide cured at 180 °C is used as a gate dielectric to fabricate flexible organic thin-film transistors with pentacene as an active semiconductor on polyethersulfone substrate. With the inherently photosensitive polyimide, the access to the gate electrode could be created easily without complicated and expensive lithographic techniques. A field effect carrier mobility of 0.007 cm2/V s was obtained for the pentacene organic thin-film transistors (OTFTs) with the photo-patterned polyimide as a gate dielectric. More detailed analysis for the pentacene OTFTs will be given with electrical properties of the thin polyimide film. Low-temperature processability and patternability of the polyimide give us more freedom to choose plastic substrates in OTFTs and facilitate the realization of low-cost organic electronics.

Defect Analysis and Reliability Characteristics of (HfZrO4)1−x(SiO2)x High-κ Dielectrics

2020 ◽  
Vol 20 (11) ◽  
pp. 6718-6722
Author(s):  
Areum Park ◽  
Pyungho Choi ◽  
Woojin Jeon ◽  
Donghyeon Lee ◽  
Donghee Choi ◽  
...  
Keyword(s):  
Silicon Oxide ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Flat Band ◽  
Defect Analysis ◽  
Positive Direction ◽  
Reliability Characteristics ◽  
Capacitance Voltage ◽  
Bias Temperature Stress ◽  
Curve Shift

Hafnium zirconium silicon oxide ((HfZrO4)1−x(SiO2)x) materials were investigated through the defect analysis and reliability characterization for next generation high-κ dielectric. Silicate doped hafnium zirconium oxide (HfZrO4) films showed a reduction of negative flat-band voltage (Vfb) shift compared to pure HfZrO4. This result was caused by a decrease in donor-like interface traps (Dit) and positive border traps (Nbt). As the silicon oxide (SiO2) content increased, the Vfb was shifted in the positive direction from −1.23 to −1.10 to −0.91 V and the slope of the capacitance–voltage (C–V) curve increased. The nonparallel shift of the C–V characteristics was affected by the Dit, while the Nbt was responsible for the parallel C–V curve shift. The values of Dit reduced from 4.3 × 1011, 3.5 × 1011, and 3.0 × 1011 cm−2eV−1, as well as the values of Nbt were decreased from 5.24, 3.90 to 2.26 × 1012 cm−2. Finally, reduction of defects in the HfZrO4-base film with an addition of SiO2 affected the gate oxide reliability characteristics, such as gate leakage current (JG), bias temperature stress instability (BTSI), and time dependent gate dielectric breakdown (TDDB).

TMCTS for gate dielectric in thin film transistors

1996 ◽  
Vol 424 ◽  
Author(s):  
Albert W. Wang ◽  
Navakanta Bhat ◽  
Krishna C. Saraswat
Keyword(s):  
Thin Film ◽  
Low Temperature ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Thin Film Transistor ◽  
Superior Performance ◽  
Stress Tests ◽  
Gate Oxides ◽  
Liquid Source ◽  
Temperature Oxide

AbstractThe use of the liquid source tetramethylcyclotetrasiloxane (TMCTS) for gate dielectric deposition in low-temperature polysilicon thin film transistor (TFT) processes is investigated. TMCTS was reacted with O2 in an LPCVD furnace at 580°C to form a gate dielectric. For comparison, a low temperature oxide (LTO) was deposited as a gate dielectric using SiH4−O2 LPCVD at 450°C. Capacitance and charge pumping measurements indicate fewer interface states for TMCTS gate dielectric. Both NMOS and PMOS TFTs show comparable or superior performance with TMCTS oxide. Post-deposition annealing has less effect on TMCTS gate oxides. Although TMCTS gate dielectrics appear slightly more susceptible to damage in biastemperature stress tests, TFTs with TMCTS gate oxides still retain better performance after stressing.

Poly-Si TFTs From Glass to Plastic Substrates: Process and Manufacturing Challenges

2004 ◽  
Vol 814 ◽  
Author(s):  
F. Lemmi ◽  
S. Lin ◽  
B.C. Drews ◽  
A. Hua ◽  
J.R. Stern ◽  
...  
Keyword(s):  
Low Temperature ◽  
Laser Annealing ◽  
Gate Dielectric ◽  
Film Stress ◽  
Superior Performance ◽  
Excimer Laser Annealing ◽  
Active Matrix ◽  
Plastic Substrates ◽  
Active Matrix Displays ◽  
Automated Tools

AbstractPoly-Si Thin-Film Transistors (TFTs) are currently used in commercial active-matrix displays. They provide superior performance with respect to their amorphous silicon counterparts and allow integration of driving electronics directly on the display glass plates.For several applications, it can be desirable to have active-matrix displays made on flexible substrates. However, a direct application of a standard TFT process to plastic substrates is not in general possible, mostly because of temperature limits and related dimensional stability issues. In addition, standard flat-panel manufacturing tools are not capable of automatically handling non-rigid floppy substrates.Therefore, a new process has to be developed, compatible with a suitable way of handling plastic substrates. A process was developed in which plastic sheets are laminated on glass carrier wafers and run through all the automated tools. A low-temperature process using excimer laser annealing is developed and optimized. High-quality TFT backplanes are manufactured with a pixel layout designed for active-matrix OLED (AMOLED) displays. Field-effect mobility in excess of 70 cm2Vs on p-channel TFTs are achieved, together with leakage currents lower than 2 pA per micron gate width.Challenges include low-temperature gate dielectric development, reduction of intrinsic film stress, protection of plastic from laser damage, and contact formation. Solutions to these challenges are discussed and TFT transfer characteristics on glass and plastic substrates are presented. Finally, images from prototype monochrome AMOLED displays are presented, with 64 × 64 pixels and 80-dpi resolution.

The Effects of Nitrogen on Electrical and Structural Properties in TaSixNy/SiO2/p-Si MOS Capacitors

2002 ◽  
Vol 716 ◽  
Author(s):  
You-Seok Suh ◽  
Greg Heuss ◽  
Jae-Hoon Lee ◽  
Veena Misra
Keyword(s):  
Structural Properties ◽  
Electron Spectroscopy ◽  
Oxygen Diffusion ◽  
Gate Dielectric ◽  
Barrier Properties ◽  
Reaction Rates ◽  
Cross Sectional ◽  
Mos Capacitors ◽  
Transmission Electron ◽  
Thermal Stability Of

AbstractIn this work, we report the effects of nitrogen on electrical and structural properties in TaSixNy /SiO2/p-Si MOS capacitors. TaSixNy films with various compositions were deposited by reactive sputtering of TaSi2 or by co-sputtering of Ta and Si targets in argon and nitrogen ambient. TaSixNy films were characterized by Rutherford backscattering spectroscopy and Auger electron spectroscopy. It was found that the workfunction of TaSixNy (Si>Ta) with varying N contents ranges from 4.2 to 4.3 eV. Cross-sectional transmission electron microscopy shows no indication of interfacial reaction or crystallization in TaSixNy on SiO2, resulting in no significant increase of leakage current in the capacitor during annealing. It is believed that nitrogen retards reaction rates and improves the chemical-thermal stability of the gate-dielectric interface and oxygen diffusion barrier properties.

A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

2009 ◽  
Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Root Cause ◽  
Gate Oxide Integrity

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

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