Defect Analysis and Reliability Characteristics of (HfZrO4)1−x(SiO2)x High-κ Dielectrics

2020 ◽  
Vol 20 (11) ◽  
pp. 6718-6722
Author(s):  
Areum Park ◽  
Pyungho Choi ◽  
Woojin Jeon ◽  
Donghyeon Lee ◽  
Donghee Choi ◽  
...  
Keyword(s):  
Silicon Oxide ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Flat Band ◽  
Defect Analysis ◽  
Positive Direction ◽  
Reliability Characteristics ◽  
Capacitance Voltage ◽  
Bias Temperature Stress ◽  
Curve Shift

Hafnium zirconium silicon oxide ((HfZrO4)1−x(SiO2)x) materials were investigated through the defect analysis and reliability characterization for next generation high-κ dielectric. Silicate doped hafnium zirconium oxide (HfZrO4) films showed a reduction of negative flat-band voltage (Vfb) shift compared to pure HfZrO4. This result was caused by a decrease in donor-like interface traps (Dit) and positive border traps (Nbt). As the silicon oxide (SiO2) content increased, the Vfb was shifted in the positive direction from −1.23 to −1.10 to −0.91 V and the slope of the capacitance–voltage (C–V) curve increased. The nonparallel shift of the C–V characteristics was affected by the Dit, while the Nbt was responsible for the parallel C–V curve shift. The values of Dit reduced from 4.3 × 1011, 3.5 × 1011, and 3.0 × 1011 cm−2eV−1, as well as the values of Nbt were decreased from 5.24, 3.90 to 2.26 × 1012 cm−2. Finally, reduction of defects in the HfZrO4-base film with an addition of SiO2 affected the gate oxide reliability characteristics, such as gate leakage current (JG), bias temperature stress instability (BTSI), and time dependent gate dielectric breakdown (TDDB).

Radiation Hardness for Silicon Oxide and Aluminum Oxide on 4H-SiC

2018 ◽  
Vol 924 ◽  
pp. 229-232 ◽  
Author(s):  
Anders Hallén ◽  
Sethu Saveda Suvanam
Keyword(s):  
Proton Irradiation ◽  
Silicon Oxide ◽  
Positive Charge ◽  
Gate Dielectric ◽  
Radiation Hardness ◽  
Flat Band ◽  
Capacitance Voltage ◽  
Cv Measurements ◽  
Radiation Hard ◽  
Mos Structures

The radiation hardness of two dielectrics, SiO2and Al2O3, deposited on low doped, n-type 4H-SiC epitaxial layers has been investigated by exposing MOS structures involving these materials to MeV proton irradiation. The samples are examined by capacitance voltage (CV) measurements and, from the flat band voltage shift, it is concluded that positive charge is induced in the exposed structures detectable for fluence above 1×1011cm-2. The positive charge increases with proton fluence, but the SiO2/4H-SiC structures are slightly more sensitive, showing that Al2O3can provide a more radiation hard passivation, or gate dielectric for 4H-SiC devices.

Low Temperature PECVD Silicon Oxide For Devices And Circuits On Flexible Substrates

2003 ◽  
Vol 769 ◽  
Author(s):  
Mark Meitine ◽  
Andrei Sazonov
Keyword(s):  
Low Temperature ◽  
Electronic Properties ◽  
Silicon Oxide ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Mos Capacitors ◽  
Plastic Substrates ◽  
Temperature Oxide ◽  
Stress Uniformity ◽  
Deposited Films

AbstractThe aim of this research is to develop low temperature gate dielectric/passivation layer for μc-Si and poly-Si based devices and circuits compatible with plastic substrates.The PECVD silicon oxide films were fabricated from mixture of silane and nitrous oxide at 250 °C, 120 °C and 75 °C. Helium, argon and nitrogen were used as diluent gases to optimize density, stress, uniformity, and electronic properties.Chemical composition and bonding in the films were studied by FTIR spectroscopy. The absorption peak at 1075-1080 cm-1 observed in the spectrum of each film corresponds to SiO2 stretching mode. No presence of SiH stretching or NH-stretching vibrations was found in the FTIR spectra of the samples.Film uniformity was varied from 1.44 % to 5.60 % for 3“×3” area. Four wafers were processed at the same time. The deposited films have compressive stress varied from 0.063 GPa to 0.117 GPa. Respective film density is in the range from 1.63 g/cm3 to 1.77 g/cm3.The electronic properties were studied on MOS capacitors with 200 nm thick SiOx. The dielectric permittivity was in the range between 2.03 and 3.57. The dielectric breakdown at 9 MV/cm was observed for the films deposited at 120 °C. The films deposited at higher temperatures are characterized by lower leakage current density, which was 3.7.10-10 A/cm2 for the sample deposited at 250 °C, 9.10-9 A/cm2 for 120 °C, and 2.2.10-8 A/cm2 for 75 °C at 5 MV/cm.The a-Si:H based TFTs were fabricated using low temperature oxide as gate dielectric. TFTs demonstrate threshold voltage (3.02 – 4.12 V) and mobility (0.12 – 0.59 cm2/Vs) comparing with those using silicon nitride.

Study on ZrO2 Deposited Directly on Si as an Alternative Gate Dielectric Material

1999 ◽  
Vol 606 ◽  
Author(s):  
Wen-Jie Qi ◽  
Renee Nieh ◽  
Byoung Hun Lee ◽  
Youngjoo Jeon ◽  
Laegu Kang ◽  
...  
Keyword(s):  
Photoelectron Spectroscopy ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Dielectric Material ◽  
Oxide Thickness ◽  
Amorphous Structure ◽  
Flat Band ◽  
Equivalent Oxide Thickness ◽  
Low Leakage ◽  
Quantum Mechanical Effects

AbstractReactive-magnetron-sputtered ZrO2 thin film has been deposited on Si directly for gate dielectric application. Both structural and electrical properties of the ZrO2 film have been investigated. An amorphous structure for 30Å ZrO2 and a semi-amorphous structure for 200Å ZrO2 have been revealed. The sputtered film shows a good stoichiometry and a good structural stability of ZrO2 based on the X-ray photoelectron spectroscopy and Rutherford backscattering spectroscopy data. Thin equivalent oxide thickness of about 11.5Å was obtained without the consideration of quantum mechanical effects. A low leakage of less than 10−2 A/cm2 at ±1V relative to the flat band voltage was obtained for this 11.5Å equivalent oxide thickness Pt/ZrO2/Si structure. High effective dielectric breakdown and superior reliability properties have been demonstrated for ZrO2 gate dielectric.

scholarly journals Electrical Characteristics and Reliability of SiCN/ Porous SiOCH Stacked Dielectric: Effects of Deposition Temperature of SiCN Film

2021 ◽  
Author(s):  
Yi-Lung Cheng ◽  
Yu-Lu Lin ◽  
Wei-Fan Peng ◽  
Chih-Yen Lee ◽  
Yow-Jon Lin
Keyword(s):  
Deposition Temperature ◽  
Silicon Oxide ◽  
Dielectric Breakdown ◽  
Semiconductor Industry ◽  
Silicon Carbonitride ◽  
Dielectric Films ◽  
Future Research ◽  
Electrical Stress ◽  
Reliability Characteristics ◽  
Different Temperatures

Abstract Silicon carbonitride (SiCN) films deposited using silazane singe-precursor with different temperatures were capped onto porous carbon-doped silicon oxide (p-SiOCH) dielectric films. Effects on the electrical and reliability characteristics of the fabricated SiCN/p-SiOCH stacked dielectrics were investigated. Experimental results indicated that increasing the deposition temperature of the SiCN film increased barrier capacity against Cu migration under thermal and electrical stress and time-dependence-dielectric-breakdown reliability for the SiCN/p-SiOCH stacked dielectric. Therefore, this study provides a promising processing to deposit a SiCN barrier by elevating the deposition temperature and using N-methyl-aza-2,2,4-trimethylsilacyclopentane singe-precursor, which can be applied to back-end-of-line interconnects for advanced technological nodes in the semiconductor industry. A larger capacitance, however, is the main issue due to a larger intrinsic dielectric constant of the SiCN film and stronger plasma-induced damage on the p-SiOCH film. As a result, the related actions will be taken in the future research to improve this issue.

Amorphous Silicon Based TFT and MIS Nonvolatile Memories

2007 ◽  
Vol 989 ◽  
Author(s):  
Yue Kuo ◽  
Helinda Nominanda
Keyword(s):  
Amorphous Silicon ◽  
Gate Dielectric ◽  
Low Cost ◽  
Flat Band ◽  
Nonvolatile Memories ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Voltage Hysteresis ◽  
A Charge ◽  
Silicon Based

AbstractThe amorphous silicon (a-Si:H) TFT and MIS capacitor, which include an a-Si:H layer embedded in the silicon nitride gate dielectric layer, have been prepared and characterized for memory functions. Large shifts of the threshold voltage and flat band voltage were detected in the current-voltage and capacitance-voltage hysteresis measurements. The embedded a-Si:H film functioned as a charge retention medium that stores and releases injected carriers. The devices memory capacity varied with the thickness of the embedded a-Si:H layer and the sweep voltage. These low-cost memory devices can be used in many low-temperature prepared circuits.

AlON/SiO2 Stacked Gate Dielectrics for 4H-SiC MIS Devices

2009 ◽  
Vol 615-617 ◽  
pp. 541-544 ◽  
Author(s):  
Takuji Hosoi ◽  
Makoto Harada ◽  
Yusuke Kagei ◽  
Yuu Watanabe ◽  
Takayoshi Shimura ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Gate Insulator ◽  
Flat Band ◽  
Aluminum Oxynitride ◽  
Fixed Charges ◽  
Interface Charge ◽  
Capacitance Voltage ◽  
High Dielectric ◽  
Mis Devices

We propose the use of an aluminum oxynitride (AlON) gate insulator for 4H-SiC MIS devices. Since direct deposition of AlON on 4H-SiC substrate generates a large amount of interface charge due to an interfacial reaction, a thick AlON layer was deposited on underlying thin SiO2 thermally grown in N2O ambient. To reduce the negative fixed charge density in the aluminum oxide (Al2O3) film, we used reactive sputtering of Al in an N2/O2 gas mixture. The fabricated MIS capacitor with AlON/SiO2 stacked gate dielectric shows no flat band voltage shift and negligible capacitance-voltage hysteresis (30 mV), indicating the dielectric is almost free from both fixed charges and electrical defects. Owing to the high dielectric constant of AlON (k=6.9), as compared to single N2O-SiO2 gate insulator, significant gate leakage reduction was achieved by AlON/SiO2 stacked gate dielectrics even at high-temperature, especially in a high electric field condition (>5 MV/cm).

A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

2009 ◽  
Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Root Cause ◽  
Gate Oxide Integrity

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

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