Electrical Characteristics of TaOxNy/ZrSixOy Stack Gate Dielectric for MOS Device Applications

2001 ◽  
Vol 670 ◽  
Author(s):  
Hyungsuk Jung ◽  
Hyundoek Yang ◽  
Kiju Im ◽  
Hyunsang Hwang
Keyword(s):  
Interfacial Layer ◽  
Silicon Oxide ◽  
Gate Dielectric ◽  
Oxide Thickness ◽  
Tem Analysis ◽  
Mos Capacitors ◽  
Zirconium Silicate ◽  
Transmission Electron ◽  
High K ◽  
Device Applications

ABSTRACTThis letter describes a unique process for the preparation of high quality tantalum oxynitride (TaOxNy) with zirconium silicate (ZrSixOy) as an interfacial layer for use in gate dielectric applications. Compared with conventional native silicon oxide and oxynitride as an interfacial layer, tantalum oxynitride (TaOxNy) MOS capacitors using zirconium silicate (ZrSixOy) as an interfacial layer exhibit lower leakage current levels at the same equivalent oxide thickness. We were able to confirm TaOxNy/ZrSixOy stack structure by auger electron spectroscopy (AES) and transmission electron microscope (TEM) analysis. The estimated dielectric constant of TaOxNy and ZrSixOywere approximately 67 and 7, respectively. The zirconium silicate is a promising interfacial layer for future high-k gate dielectric applications.

Scalability of MOCVD-deposited Hafnium Oxide

2003 ◽  
Vol 765 ◽  
Author(s):  
S. Van Elshocht ◽  
R. Carter ◽  
M. Caymax ◽  
M. Claes ◽  
T. Conard ◽  
...  
Keyword(s):  
Hafnium Oxide ◽  
Interfacial Layer ◽  
Gate Dielectric ◽  
Deposition Process ◽  
Oxide Thickness ◽  
Process Conditions ◽  
Primary Concern ◽  
Gate Electrode ◽  
K Value ◽  
High K

AbstractBecause of aggressive downscaling to increase transistor performance, the physical thickness of the SiO2 gate dielectric is rapidly approaching the limit where it will only consist of a few atomic layers. As a consequence, this will result in very high leakage currents due to direct tunneling. To allow further scaling, materials with a k-value higher than SiO2 (“high-k materials”) are explored, such that the thickness of the dielectric can be increased without degrading performance.Based on our experimental results, we discuss the potential of MOCVD-deposited HfO2 to scale to (sub)-1-nm EOTs (Equivalent Oxide Thickness). A primary concern is the interfacial layer that is formed between the Si and the HfO2, during the MOCVD deposition process, for both H-passivated and SiO2-like starting surfaces. This interfacial layer will, because of its lower k-value, significantly contribute to the EOT and reduce the benefit of the high-k material. In addition, we have experienced serious issues integrating HfO2 with a polySi gate electrode at the top interface depending on the process conditions of polySi deposition and activation anneal used. Furthermore, we have determined, based on a thickness series, the k-value for HfO2 deposited at various temperatures and found that the k-value of the HfO2 depends upon the gate electrode deposited on top (polySi or TiN).Based on our observations, the combination of MOCVD HfO2 with a polySi gate electrode will not be able to scale below the 1-nm EOT marker. The use of a metal gate however, does show promise to scale down to very low EOT values.

Limiting Native Oxide Regrowth for High-k Gate Dielectrics

2003 ◽  
Vol 765 ◽  
Author(s):  
K. Choi ◽  
H. Harris ◽  
S. Gangopadhyay ◽  
H. Temkin
Keyword(s):  
Silicon Oxide ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Oxide Thickness ◽  
Hafnium Dioxide ◽  
Electron Beam Evaporation ◽  
Native Oxide ◽  
Device Applications ◽  
The Difference ◽  
Cleaning Methods

AbstractA cleaning process resulting in atomically smooth, hydrogen-terminated, silicon surface that would inhibit formation of native silicon oxide is needed for high-k gate dielectric deposition. Various cleaning methods thus need to be tested in terms of resistance to native oxide formation. Native oxide re-growth is studied as a function of exposure time to atmospheric ambient using ellipsometry. Hafnium dioxide film (k ~23) is deposited on the as-cleaned substrates by electron beam evaporation and subsequently annealed in hydrogen. The difference in the effective oxide thickness re-grown on surfaces treated with the conventional RCA and modified Shiraki cleaning methods, after one-hour exposure, can be as large as 2 Å. This is significant in device applications demanding equivalent oxide thickness less than 20 Å. The degree of hydrogen passivation, surface micro-roughness and organic removal capability are considered to be the main factors that explain the differences between the cleaning methods. Data derived from capacitance-voltage analysis of test capacitors verified the trend observed in the native oxide thickness measurements. An increase of 10~15 % in accumulation capacitance is observed in the samples treated by the new cleaning method.

Highly Reliable Thin Hafnium Oxide Gate Dielectric

1999 ◽  
Vol 592 ◽  
Author(s):  
Laegu Kang ◽  
Byoung-Hun Lee ◽  
Wen-Jie Qi ◽  
Yong-Joo Jeon ◽  
Renee Nieh ◽  
...  
Keyword(s):  
Hafnium Oxide ◽  
Interfacial Layer ◽  
Gate Dielectric ◽  
Frequency Dispersion ◽  
Deposition Process ◽  
Oxide Thickness ◽  
Mos Capacitors ◽  
Control Interface ◽  
High Resolution Tem ◽  
The One

ABSTRACTHfO2 is the one of the potential high-k dielectrics for replacing SiO2 as a gate dielectric. HfO2 is thermodynamically stable when in direct contact with Si and has a reasonable band gap (∼5.65eV). In this study, MOS capacitors (Pt/HfO2/Si) were fabricated by depositing HfO2 using reactive DC magnetron sputtering in the range of 33∼135Å followed by Pt deposition. During the HfO2 deposition, O2 flow was modulated to control interface quality and to suppress interfacial layer growing. By optimizing the HfO2 deposition process, equivalent oxide thickness (EOT) can be reduced down to ∼11.2 Å with the leakage current as low as 1X10−2 A/cm2 at +1.0V and negligible frequency dispersion. HfO2 films also show excellent breakdown characteristics and negligible hysteresis after high temperature annealing. From the high resolution TEM, there is a thin interfacial layer after annealing, suggesting a composite of Si-Hf-O with a dielectric constant of ≈ 2 X K SiO2.

The Effects of Nitrogen on Electrical and Structural Properties in TaSixNy/SiO2/p-Si MOS Capacitors

2002 ◽  
Vol 716 ◽  
Author(s):  
You-Seok Suh ◽  
Greg Heuss ◽  
Jae-Hoon Lee ◽  
Veena Misra
Keyword(s):  
Structural Properties ◽  
Electron Spectroscopy ◽  
Oxygen Diffusion ◽  
Gate Dielectric ◽  
Barrier Properties ◽  
Reaction Rates ◽  
Cross Sectional ◽  
Mos Capacitors ◽  
Transmission Electron ◽  
Thermal Stability Of

AbstractIn this work, we report the effects of nitrogen on electrical and structural properties in TaSixNy /SiO2/p-Si MOS capacitors. TaSixNy films with various compositions were deposited by reactive sputtering of TaSi2 or by co-sputtering of Ta and Si targets in argon and nitrogen ambient. TaSixNy films were characterized by Rutherford backscattering spectroscopy and Auger electron spectroscopy. It was found that the workfunction of TaSixNy (Si>Ta) with varying N contents ranges from 4.2 to 4.3 eV. Cross-sectional transmission electron microscopy shows no indication of interfacial reaction or crystallization in TaSixNy on SiO2, resulting in no significant increase of leakage current in the capacitor during annealing. It is believed that nitrogen retards reaction rates and improves the chemical-thermal stability of the gate-dielectric interface and oxygen diffusion barrier properties.

Nitrogen (N2) Implantation to Suppress Growth of Interfacial Oxide in Mocvd Bst and Sputtered Bst Films

1999 ◽  
Vol 567 ◽  
Author(s):  
Renee Nieh ◽  
Wen-Jie Qi ◽  
Yongjoo Jeon ◽  
Byoung Hun Lee ◽  
Aaron Lucas ◽  
...  
Keyword(s):  
Photoelectron Spectroscopy ◽  
Interfacial Layer ◽  
Gate Dielectric ◽  
Nitrogen Concentration ◽  
Chemical Vapor ◽  
Future Generation ◽  
Oxide Thickness ◽  
Layer Growth ◽  
X Ray ◽  
Bst Films

ABSTRACTBa0.5Sr0.5TiO3 (BST) is one of the high-k candidates for replacing SiO2 as the gate dielectric in future generation devices. The biggest obstacle to scaling the equivalent oxide thickness (EOT) of BST is an interfacial layer, SixOy, which forms between BST and Si. Nitrogen (N2) implantation into the Si substrate has been proposed to reduce the growth of this interfacial layer. In this study, capacitors (Pt/BST/Si) were fabricated by depositing thin BST films (50Å) onto N2 implanted Si in order to evaluate the effects of implant dose and annealing conditions on EOT. It was found that N2 implantation reduced the EOT of RF magnetron sputtered and Metal Oxide Chemical Vapor Deposition (MOCVD) BST films by ∼20% and ∼33%, respectively. For sputtered BST, an implant dose of 1×1014cm−;2 provided sufficient nitrogen concentration without residual implant damage after annealing. X-ray photoelectron spectroscopy data confirmed that the reduction in EOT is due to a reduction in the interfacial layer growth. X-ray diffraction spectra revealed typical polycrystalline structure with (111) and (200) preferential orientations for both films. Leakage for these 50Å BST films is on the order of 10−8 to 10−5 A/cm2—lower than oxynitrides with comparable EOTs.

scholarly journals Current Tunnelling in MOS Devices with Al2O3/SiO2 Gate Dielectric

2008 ◽  
Vol 2008 ◽  
pp. 1-5 ◽  
Author(s):  
A. Bouazra ◽  
S. Abdi-Ben Nasrallah ◽  
M. Said ◽  
A. Poncet
Keyword(s):  
Dielectric Constant ◽  
Gate Dielectric ◽  
Oxide Thickness ◽  
Gate Leakage ◽  
Mos Devices ◽  
High K ◽  
Carrier Trap ◽  
High Dielectric ◽  
Very High ◽  
Tunnelling Current

With the continued scaling of the SiO2 thickness below 2 nm in CMOS devices, a large direct-tunnelling current flow between the gate electrode and silicon substrate is greatly impacting device performance. Therefore, higher dielectric constant materials are desirable for reducing the gate leakage while maintaining transistor performance for very thin dielectric layers. Despite its not very high dielectric constant (∼10), Al2O3 has emerged as one of the most promising high-k candidates in terms of its chemical and thermal stability as its high-barrier offset. In this paper, a theoretical study of the physical and electrical properties of Al2O3 gate dielectric is reported including I(V) and C(V) characteristics. By using a stack of Al2O3/SiO2 with an appropriate equivalent oxide thickness of gate dielectric MOS, the gate leakage exhibits an important decrease. The effect of carrier trap parameters (depth and width) at the Al2O3/SiO2 interface is also discussed.

Oxide Impurities in Silicon Oxide Intermetal Dielectrics and Their Potential to Elevate Via-Resistances

2014 ◽  
Vol 20 (4) ◽  
pp. 1271-1275 ◽  
Author(s):  
Wentao Qin ◽  
Donavan Alldredge ◽  
Douglas Heleotes ◽  
Alexander Elkind ◽  
N. David Theodore ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Transmission Electron Microscopy ◽  
Vapor Deposition ◽  
Physical Vapor Deposition ◽  
Silicon Oxide ◽  
Atomic Ratio ◽  
Tem Analysis ◽  
Transmission Electron ◽  
Layer Deposition ◽  
Intermetal Dielectric

AbstractSilicon oxide used as an intermetal dielectric (IMD) incorporates oxide impurities during both its formation and subsequent processing to create vias in the IMD. Without a sufficient degassing of the IMD, oxide impurities released from the IMD during the physical vapor deposition (PVD) of the glue layer of the vias had led to an oxidation of the glue layer and eventual increase of the via resistances, which correlated with the O-to-Si atomic ratio of the IMD being ~10% excessive as verified by transmission electron microscopy (TEM) analysis. A vacuum bake of the IMD was subsequently implemented to enhance outgassing of the oxide impurities in the IMD before the glue layer deposition. The implementation successfully reduced the via resistances to an acceptable level.

High quality, high-k gate dielectric: amorphous LaAlO3 thin films grown on Si(100) without Si interfacial layer

2003 ◽  
Vol 77 (5) ◽  
pp. 721-724 ◽  
Author(s):  
L. Yan ◽  
H.B. Lu ◽  
G.T. Tan ◽  
F. Chen ◽  
Y.L. Zhou ◽  
...  
Keyword(s):  
Thin Films ◽  
Interfacial Layer ◽  
Gate Dielectric ◽  
High Quality ◽  
High K ◽  
High K Gate Dielectric

Optimization of UHV-CVD Thin Films for Gate Dielectric Applications

2006 ◽  
Vol 45 ◽  
pp. 1351-1354
Author(s):  
Bridget R. Rogers ◽  
Zhe Song ◽  
Robert D. Geil ◽  
Robert A. Weller
Keyword(s):  
Silicon Oxide ◽  
Gate Dielectric ◽  
High Surface ◽  
Ex Situ ◽  
Oxide Surfaces ◽  
Layer By Layer ◽  
Force Microscopy ◽  
Transmission Electron ◽  
Initial Stage ◽  
Different Temperatures

In-situ and ex-situ spectroscopic ellipsometry (SE), atomic force microscopy (AFM), transmission electron microscopy (TEM), and time of flight medium energy backscattering (ToF MEBS), are used to investigate the properties of 30 and 60 Å ZrO2 films deposited at different temperatures on hydrogen terminated silicon (H-Si) and native silicon oxide surfaces. Results show that the initial-stage deposition of ZrO2 on H-Si and native silicon oxide surfaces are different. A 3-dimesional (3D) type nucleation process of ZrO2 on H-Si leads to high surface roughness films, while layer-by-layer deposition on native silicon oxide surfaces leads to smooth, uniform ZrO2 films. An interfacial layer, between the substrate and the metal oxide, is formed through two independent mechanisms: reaction between the starting surfaces and ZTB or its decomposition intermediates, and diffusion of reactive oxidants through the forming ZrO2 interfacial stack layer to react with the substrate.

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