Optimization of Poly-SiGe Deposition Processes for Modular MEMS Integration

2003 ◽  
Vol 782 ◽  
Author(s):  
Blake C.-Y. Lin ◽  
Tsu-Jae King ◽  
Roger T. Howe
Keyword(s):  
Strain Gradient ◽  
Silicon Germanium ◽  
Polycrystalline Silicon ◽  
Radius Of Curvature ◽  
Post Deposition Annealing ◽  
Thermal Budget ◽  
Layer Deposition ◽  
Layer Technique ◽  
Deposition Processes ◽  
Post Deposition

ABSTRACTThis paper describes a bi-layer deposition technique to reduce the strain gradient of polycrystalline silicon-germanium (poly-SiGe) thin films without the use of any post-deposition annealing. By adjusting deposition conditions such as temperature, pressure, and/or flow rates of reactants, poly-SiGe films with required low average stresses can be obtained. Using the bi-layer technique, a strain gradient of 1.1×10-5 μm-1 (equivalent to 88 mm radius-of-curvature) has been achieved in 3.9 μm-thick poly-SiGe. This strain gradient would cause only 0.055 μm tip deflection for a 100 μm-long cantilever. The thermal budget was ∼10 hours at 425 °C, and no post-deposition annealing was required. The bi-layer film also exhibits low compressive average stress (-36 MPa) and low resistivity (0.55 mΩ-cm).

Low-Temperature LPCVD MEMS Technologies

2002 ◽  
Vol 729 ◽  
Author(s):  
Roger T. Howe ◽  
Tsu-Jae King
Keyword(s):  
Silicon Germanium ◽  
Polycrystalline Silicon ◽  
Rf Mems ◽  
Sige Layer ◽  
Copper Metallization ◽  
Si Films ◽  
P Type ◽  
Mems Process ◽  
Post Deposition

AbstractThis paper describes recent research on LPCVD processes for the fabrication of high-quality micro-mechanical structures on foundry CMOS wafers. In order to avoid damaging CMOS electronics with either aluminum or copper metallization, the MEMS process temperatures should be limited to a maximum of 450°C. This constraint rules out the conventional polycrystalline silicon (poly-Si) as a candidate structural material for post-CMOS integrated MEMS. Polycrystalline silicon-germanium (poly-SiGe) alloys are attractive for modular integration of MEMS with electronics, because they can be deposited at much lower temperatures than poly-Si films, yet have excellent mechanical properties. In particular, in-situ doped p-type poly-SiGe films deposit rapidly at low temperatures and have adequate conductivity without post-deposition annealing. Poly-Ge can be etched very selectively to Si, SiGe, SiO2 and Si3N4 in a heated hydrogen peroxide solution, and can therefore be used as a sacrificial material to eliminate the need to protect the CMOS electronics during the MEMS-release etch. Low-resistance contact between a structural poly-SiGe layer and an underlying CMOS metal interconnect can be accomplished by deposition of the SiGe onto a typical barrier metal exposed in contact windows. We conclude with directions for further research to develop poly-SiGe technology for integrated inertial, optical, and RF MEMS applications.

Effects of Post-Deposition Annealing on the Electrical Properties of HfSiO Films Grown by Atomic Layer Deposition

2005 ◽  
Vol 44 (4B) ◽  
pp. 2230-2234 ◽  
Author(s):  
Hag-Ju Cho ◽  
Hye Lan Lee ◽  
Hong Bae Park ◽  
Taek Soo Jeon ◽  
Seong Geon Park ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Atomic Layer Deposition ◽  
Atomic Layer ◽  
Post Deposition Annealing ◽  
Layer Deposition ◽  
Post Deposition

Atomic layer deposition and post-deposition annealing of PbTiO3 thin films

2006 ◽  
Vol 496 (2) ◽  
pp. 346-352 ◽  
Author(s):  
Jenni Harjuoja ◽  
Anne Kosola ◽  
Matti Putkonen ◽  
Lauri Niinistö
Keyword(s):  
Thin Films ◽  
Atomic Layer Deposition ◽  
Atomic Layer ◽  
Post Deposition Annealing ◽  
Layer Deposition ◽  
Post Deposition

Manganese oxide films with controlled oxidation state for water splitting devices through a combination of atomic layer deposition and post-deposition annealing

RSC Advances ◽  
2016 ◽  
Vol 6 (100) ◽  
pp. 98337-98343 ◽  
Author(s):  
Felix Mattelaer ◽  
Tom Bosserez ◽  
Jan Rongé ◽  
Johan A. Martens ◽  
Jolien Dendooven ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Films ◽  
Atomic Layer Deposition ◽  
Manganese Oxide ◽  
Atomic Layer ◽  
Post Deposition Annealing ◽  
Solar Hydrogen ◽  
Layer Deposition ◽  
Thin Film Catalysts ◽  
Post Deposition

Manganese oxide thin films were obtained by a combination of atomic layer deposition and post-deposition annealing, and the viability of these thin films as thin film catalysts for solar hydrogen devices has been demonstrated.

Interval Annealing During Alternating Pulse Deposition

2004 ◽  
Vol 811 ◽  
Author(s):  
J.F. Conley ◽  
D.J. Tweet ◽  
Y. Ono ◽  
G. Stecker
Keyword(s):  
Thin Films ◽  
Interfacial Layer ◽  
Bulk Material ◽  
Atomic Layer ◽  
Post Deposition Annealing ◽  
Equivalent Thickness ◽  
Layer Deposition ◽  
Pulse Deposition ◽  
Post Deposition

AbstractThin films deposited via atomic layer deposition at low temperature tend to be less dense than bulk material and typically require high temperature post deposition annealing for densification and removal of unreacted precursor ligands. We have found that improved film densification can be achieved by interval annealing, in which in-situ moderate temperature (∼420°C) rapid thermal anneals are performed after every n deposition cycles. HfO2 film density and refractive index were found to increase with decreasing anneal interval (more frequent annealing). The highest density films could be achieved only by every-cycle annealing and could not be achieved by post deposition annealing. The densified every cycle annealed films have been shown to have improved equivalent thickness and leakage and decreased interfacial layer thickness.

Epitaxial Realignment of In-Situ Doped Polycrystalline Silicon for Advanced BiCMOS Technologies

1999 ◽  
Vol 587 ◽  
Author(s):  
K. Chang ◽  
S.G. Thomas ◽  
T-C. Lee ◽  
R.B. Gregory ◽  
D. O'meara ◽  
...  
Keyword(s):  
Polycrystalline Silicon ◽  
Chemical Vapor ◽  
Layer Growth ◽  
Native Oxide ◽  
Post Deposition Annealing ◽  
Si Substrates ◽  
Si Films ◽  
Post Deposition

AbstractIndustrial feasibility of an in-situ-doped (ISD) polycrystalline Si process using chemical vapor deposition for advanced BiCMOS technologies is presented. ISD As-doped amorphous and polycrystalline Si layers have been deposited on Si substrates at 610°C and 660°C, respectively, with the deposition rate varying from 120 to 128Å /minute. Samples are compared on the basis of having been subjected to a substrate preclean prior to deposition using an HF solution and an in-situ H2 bake. TEM micrographs reveal the presence of a thin (10-15 Å) native oxide at the deposited layer/substrate interface for samples not precleaned. This is confirmed for both the amorphous and polycrystalline Si depositions. However, for the 610°C-deposited samples given the substrate preclean, a polycrystalline structure with partial epitaxial layer growth is observed. Twins and stacking faults are found at the poly Si/single crystal Si interface, causing interfacial roughness. Post-deposition annealing of the Si films typically generates grain growth, but RBS-channeling characterization of the annealed Si provides evidence of some recrystallization, the extent of which is affected by the original growth condition. Analysis shows that the amorphous deposition at 610°C results in a mixture of epitaxial and polycrystalline Si. Epitaxial realignment of the polycrystalline Si film by post deposition annealing can result in significantly improved device performance.

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