Low-Temperature LPCVD MEMS Technologies

2002 ◽  
Vol 729 ◽  
Author(s):  
Roger T. Howe ◽  
Tsu-Jae King
Keyword(s):  
Silicon Germanium ◽  
Polycrystalline Silicon ◽  
Rf Mems ◽  
Sige Layer ◽  
Copper Metallization ◽  
Si Films ◽  
P Type ◽  
Mems Process ◽  
Post Deposition

AbstractThis paper describes recent research on LPCVD processes for the fabrication of high-quality micro-mechanical structures on foundry CMOS wafers. In order to avoid damaging CMOS electronics with either aluminum or copper metallization, the MEMS process temperatures should be limited to a maximum of 450°C. This constraint rules out the conventional polycrystalline silicon (poly-Si) as a candidate structural material for post-CMOS integrated MEMS. Polycrystalline silicon-germanium (poly-SiGe) alloys are attractive for modular integration of MEMS with electronics, because they can be deposited at much lower temperatures than poly-Si films, yet have excellent mechanical properties. In particular, in-situ doped p-type poly-SiGe films deposit rapidly at low temperatures and have adequate conductivity without post-deposition annealing. Poly-Ge can be etched very selectively to Si, SiGe, SiO2 and Si3N4 in a heated hydrogen peroxide solution, and can therefore be used as a sacrificial material to eliminate the need to protect the CMOS electronics during the MEMS-release etch. Low-resistance contact between a structural poly-SiGe layer and an underlying CMOS metal interconnect can be accomplished by deposition of the SiGe onto a typical barrier metal exposed in contact windows. We conclude with directions for further research to develop poly-SiGe technology for integrated inertial, optical, and RF MEMS applications.

Epitaxial Realignment of In-Situ Doped Polycrystalline Silicon for Advanced BiCMOS Technologies

1999 ◽  
Vol 587 ◽  
Author(s):  
K. Chang ◽  
S.G. Thomas ◽  
T-C. Lee ◽  
R.B. Gregory ◽  
D. O'meara ◽  
...  
Keyword(s):  
Polycrystalline Silicon ◽  
Chemical Vapor ◽  
Layer Growth ◽  
Native Oxide ◽  
Post Deposition Annealing ◽  
Si Substrates ◽  
Si Films ◽  
Post Deposition

AbstractIndustrial feasibility of an in-situ-doped (ISD) polycrystalline Si process using chemical vapor deposition for advanced BiCMOS technologies is presented. ISD As-doped amorphous and polycrystalline Si layers have been deposited on Si substrates at 610°C and 660°C, respectively, with the deposition rate varying from 120 to 128Å /minute. Samples are compared on the basis of having been subjected to a substrate preclean prior to deposition using an HF solution and an in-situ H2 bake. TEM micrographs reveal the presence of a thin (10-15 Å) native oxide at the deposited layer/substrate interface for samples not precleaned. This is confirmed for both the amorphous and polycrystalline Si depositions. However, for the 610°C-deposited samples given the substrate preclean, a polycrystalline structure with partial epitaxial layer growth is observed. Twins and stacking faults are found at the poly Si/single crystal Si interface, causing interfacial roughness. Post-deposition annealing of the Si films typically generates grain growth, but RBS-channeling characterization of the annealed Si provides evidence of some recrystallization, the extent of which is affected by the original growth condition. Analysis shows that the amorphous deposition at 610°C results in a mixture of epitaxial and polycrystalline Si. Epitaxial realignment of the polycrystalline Si film by post deposition annealing can result in significantly improved device performance.

On the Temperature Dependence of Resistivity of Polycrystalline Silicon Films

1987 ◽  
Vol 106 ◽  
Author(s):  
Mark S. Rodder ◽  
Dimitri A. Antoniadis
Keyword(s):  
Numerical Calculation ◽  
Polycrystalline Silicon ◽  
Amorphous Region ◽  
Defect States ◽  
Temperature Dependent ◽  
Step Process ◽  
Dependent Potential ◽  
Si Films ◽  
Polycrystalline Silicon Films ◽  
P Type

ABSTRACTIt is shown that the grain boundary (GB) in polycrystalline-silicon (poly-Si) films need not be modeled as a temperature-dependent potential barrier or as an amorphous region to explain the temperature (T) dependence of resistivity (ρ) in p-type poly-Si films at low T. Specifically, we consider that QB defect states allow for the tunneling component of current to occur by a two-step process. Incorporation of the two-step process in a numerical calculation of ρ vs. T results in excellent agreement with available data from 100 K to 300 K.

Comparison of boron precipitation in p-type bulk nanostructured and polycrystalline silicon germanium alloy

2013 ◽  
Vol 113 (14) ◽  
pp. 143715 ◽  
Author(s):  
Zahra Zamanipour ◽  
Jerzy S. Krasinski ◽  
Daryoosh Vashaee
Keyword(s):  
Silicon Germanium ◽  
Polycrystalline Silicon ◽  
Germanium Alloy ◽  
P Type

Optimization of Poly-SiGe Deposition Processes for Modular MEMS Integration

2003 ◽  
Vol 782 ◽  
Author(s):  
Blake C.-Y. Lin ◽  
Tsu-Jae King ◽  
Roger T. Howe
Keyword(s):  
Strain Gradient ◽  
Silicon Germanium ◽  
Polycrystalline Silicon ◽  
Radius Of Curvature ◽  
Post Deposition Annealing ◽  
Thermal Budget ◽  
Layer Deposition ◽  
Layer Technique ◽  
Deposition Processes ◽  
Post Deposition

ABSTRACTThis paper describes a bi-layer deposition technique to reduce the strain gradient of polycrystalline silicon-germanium (poly-SiGe) thin films without the use of any post-deposition annealing. By adjusting deposition conditions such as temperature, pressure, and/or flow rates of reactants, poly-SiGe films with required low average stresses can be obtained. Using the bi-layer technique, a strain gradient of 1.1×10-5 μm-1 (equivalent to 88 mm radius-of-curvature) has been achieved in 3.9 μm-thick poly-SiGe. This strain gradient would cause only 0.055 μm tip deflection for a 100 μm-long cantilever. The thermal budget was ∼10 hours at 425 °C, and no post-deposition annealing was required. The bi-layer film also exhibits low compressive average stress (-36 MPa) and low resistivity (0.55 mΩ-cm).

Deposition and Characterization of In-Situ Boron Doped Polycrystalline Silicon Films for Microelectromechanical Systems Applications

1999 ◽  
Vol 605 ◽  
Author(s):  
J. J. McMahon ◽  
J. J. McMahon ◽  
J. M. Melzak ◽  
C. A. Zorman ◽  
J. Chung ◽  
...  
Keyword(s):  
Polycrystalline Silicon ◽  
Microelectromechanical Systems ◽  
Single Step ◽  
Boron Doped ◽  
Polysilicon Films ◽  
Polycrystalline Silicon Films ◽  
P Type ◽  
Deposition Conditions

AbstractIn an effort to develop thick, p-type polycrystalline silicon (polysilicon) films for microelectromechanical systems (MEMS) applications, in-situ boron-doped polysilicon films were deposited by a single-step APCVD process at susceptor temperatures ranging from 700°C to 955°C. The process produces boron-doped films at a deposition rate of 73 nm/min at 955°C. Spreading resistance measurements show that the boron doping level is constant at 2 × 1019 /cm3 throughout the thickness of the films. Doped films deposited at the low temperatures exhibit compressive stress as high as 666 Mpa; however films deposited at 955°C exhibited stress as low as 130 MPa. TEM and XRD show that the microstructure strongly depends on the deposition conditions. Surface micromachined, singly clamped cantilevers and strain gauges were successfully fabricated and used to characterize the residual stress of 5.0 µm-thick doped films deposited at a susceptor temperature of 955°C.

Photoconductive Polycrystalline Silicon Films on Glass Obtained by Hot-Wire CVD

1996 ◽  
Vol 420 ◽  
Author(s):  
A. R. Middya ◽  
J. Guillet ◽  
J. Perrin ◽  
J. E. Bouree
Keyword(s):  
Polycrystalline Silicon ◽  
Chemical Vapour ◽  
Columnar Structure ◽  
Silicon Films ◽  
High Deposition Rate ◽  
Hot Wire ◽  
Si Films ◽  
Polycrystalline Silicon Films ◽  
Deposited Films

AbstractTextured polycrystalline silicon films with columnar structure have been deposited on glass at low temperature (400–550°C) and high deposition rate (10 to 15 Å/s) by hot-wire chemical vapour deposition using SiH4-H2 gases. The homogeneity of the deposited layer is ± 5% on a 8 cm diameter. As deposited films have a poor photoconductivity. However hydrogen confinement in the films during the deposition or after the deposition is found to be the key for obtaining g.tc/poly-Si with a significant diffusion length. Eventually reasonable values of the mobility lifetime product (> 10−7 cm2/V) are obtained by in situ hydrogen passivation of poly-Si films after deposition. Efficient shifting of the Fermi level is achieved by in situ B or P doping. The incorporation of boron in poly-Si network strongly influences the morphology and the crystalline structure. Undoped films have a Hall mobility of 14 ± 5 cm2/V.s which decreases versus the carrier concentration.

Interface morphology of thermal oxide grown on polycrystalline silicon by different processes

1992 ◽  
Vol 50 (2) ◽  
pp. 1396-1397
Author(s):  
H. Yen ◽  
E. P. Kvam ◽  
R. Bashir ◽  
S. Venkatesan ◽  
G. W. Neudeck
Keyword(s):  
Integrated Circuits ◽  
Polycrystalline Silicon ◽  
Silicon Films ◽  
Interface Morphology ◽  
Oxide Interface ◽  
Poly Silicon ◽  
Thermal Oxide ◽  
Grain Orientations ◽  
Polycrystalline Silicon Films ◽  
P Type

Polycrystalline silicon, when highly doped, is commonly used in microelectronics applications such as gates and interconnects. The packing density of integrated circuits can be enhanced by fabricating multilevel polycrystalline silicon films separated by insulating SiO2 layers. It has been found that device performance and electrical properties are strongly affected by the interface morphology between polycrystalline silicon and SiO2. As a thermal oxide layer is grown, the poly silicon is consumed, and there is a volume expansion of the oxide relative to the atomic silicon. Roughness at the poly silicon/thermal oxide interface can be severely deleterious due to stresses induced by the volume change during oxidation. Further, grain orientations and grain boundaries may alter oxidation kinetics, which will also affect roughness, and thus stress.Three groups of polycrystalline silicon films were deposited by LPCVD after growing thermal oxide on p-type wafers. The films were doped with phosphorus or arsenic by three different methods.

Properties of Sputter Deposited ZnO Films Co-doped with Lithium and Phosphorus

2013 ◽  
Vol 1494 ◽  
pp. 77-82
Author(s):  
T. N. Oder ◽  
A. Smith ◽  
M. Freeman ◽  
M. McMaster ◽  
B. Cai ◽  
...  
Keyword(s):  
Rf Magnetron Sputtering ◽  
Zno Films ◽  
X Ray Diffraction ◽  
X Ray ◽  
Sapphire Substrates ◽  
Hall Effect Measurements ◽  
Sputter Deposited ◽  
P Type ◽  
Post Deposition ◽  
Co Doped

ABSTRACTThin films of ZnO co-doped with lithium and phosphorus were deposited on sapphire substrates by RF magnetron sputtering. The films were sequentially deposited from ultra pure ZnO and Li3PO4 solid targets. Post deposition annealing was carried using a rapid thermal processor in O2 and N2 at temperatures ranging from 500 °C to 1000 °C for 3 min. Analyses performed using low temperature photoluminescence spectroscopy measurements reveal luminescence peaks at 3.359, 3.306, 3.245 eV for the co-doped samples. The x-ray diffraction 2θ-scans for all the films showed a single peak at about 34.4° with full width at half maximum of about 0.17°. Hall Effect measurements revealed conductivities that change from p-type to n-type over time.

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