4H-SiC MOSFETs Using Thermal Oxidized Ta2Si Films as High-k Gate Dielectric

2005 ◽  
Vol 483-485 ◽  
pp. 713-716 ◽  
Author(s):  
Amador Pérez-Tomás ◽  
Phillippe Godignon ◽  
Narcis Mestres ◽  
Josep Montserrat ◽  
José Millan
Keyword(s):  
Dielectric Constant ◽  
Dielectric Layer ◽  
Room Temperature ◽  
Gate Dielectric ◽  
Gate Insulator ◽  
High K ◽  
Dry Oxidation ◽  
High K Dielectric ◽  
Si Films ◽  
Mis Capacitors

Oxidized Ta2Si layers have been used as high-k dielectric layer for 4H-SiC MOSFETs. The gate insulator was grown by dry oxidation of 40nm deposited Ta2Si during 1h at 1050oC. The dielectric constant obtained from 4H-SiC MIS capacitors is ~20 with an insulator thickness of 150nm. These devices exhibit adequate subthreshold, saturation and drive characteristics. For the MOSFETs fabricated on a p-implanted and annealed region, a peak mobility up to 45cm2/Vs has been extracted. The specific on-resistance of this device is 29mW·cm2 at room temperature with VDS=0.2V and VGS=14V.

Atomistic prediction on the configuration- and temperature-dependent dielectric constant of Be0.25Mg0.75O superlattice as a high-κ dielectric layer

2021 ◽  
Author(s):  
Gyuseung Han ◽  
In Won Yeu ◽  
Kun Hee Ye ◽  
Seung-Cheol Lee ◽  
Cheol Seong Hwang ◽  
...  
Keyword(s):  
Dielectric Constant ◽  
Dft Calculations ◽  
Bond Length ◽  
Dielectric Layer ◽  
Room Temperature ◽  
High Dielectric Constant ◽  
Temperature Dependent ◽  
High Dielectric

Through DFT calculations, a Be0.25Mg0.75O superlattice having long apical Be–O bond length is proposed to have a high bandgap (>7.3 eV) and high dielectric constant (∼18) at room temperature and above.

Flexible terahertz modulators based on graphene FET with organic high-k dielectric layer

2018 ◽  
Vol 5 (11) ◽  
pp. 115607
Author(s):  
Yu-Lian He ◽  
Jing-Bo Liu ◽  
Tian-Long Wen ◽  
Qing-Hui Yang ◽  
Zheng Feng ◽  
...  
Keyword(s):  
Dielectric Layer ◽  
High K ◽  
High K Dielectric ◽  
Graphene Fet

New Perovskite Nanomaterials and Their Integrations into High-k Dielectrics

2011 ◽  
Vol 2011 (CICMT) ◽  
pp. 000072-000077
Author(s):  
Minoru Osada ◽  
Takayoshi Sasaki
Keyword(s):  
Dielectric Properties ◽  
Room Temperature ◽  
Bottom Electrode ◽  
Dielectric Constants ◽  
Dielectric Films ◽  
Layered Perovskite ◽  
Layer By Layer ◽  
High K ◽  
High K Dielectric ◽  
High Dielectric

We report on a bottom-up manufacturing for high-k dielectric films using a novel nanomaterial, namely, a perovskite nanosheet (LaNb2O7) derived from a layered perovskite by exfoliation. Solution-based layer-by-layer assembly of perovskite nanosheets is effective for room-temperature fabrication of high-k nanocapacitors, which are directly assembled on a SrRuO3 bottom electrode with an atomically sharp interface. These nanocapacitors exhibit high dielectric constants (k > 50) for thickness down to 5 nm while eliminating problems resulting from the size effect. We also investigate dielectric properties of perovskite nanosheets with different compositions (LaNb2O7, La0.95Eu0.05Nb2O7, and Eu0.56Ta2O7) in order to study the influence of A- and B-site modifications on dielectric properties.

scholarly journals Impact of Hydrogen Bonds Limited Dipolar Disorder in High-k Polymer Gate Dielectric on Charge Carrier Transport in OFET

Polymers ◽  
2020 ◽  
Vol 12 (4) ◽  
pp. 826
Author(s):  
Bartosz Paruzel ◽  
Jiří Pfleger ◽  
Jiří Brus ◽  
Miroslav Menšík ◽  
Francesco Piana ◽  
...  
Keyword(s):  
Hydrogen Bonds ◽  
Charge Carrier ◽  
Charge Transport ◽  
Density Of States ◽  
Dielectric Layer ◽  
Carrier Transport ◽  
Gate Dielectric ◽  
Field Effect Transistors ◽  
Semiconductor Layer ◽  
High K

The paper contributes to the characterization and understanding the mutual interactions of the polar polymer gate dielectric and organic semiconductor in organic field effect transistors (OFETs). It has been shown on the example of cyanoethylated polyvinylalcohol (CEPVA), the high-k dielectric containing strong polar side groups, that the conditions during dielectric layer solidification can significantly affect the charge transport in the semiconductor layer. In contrast to the previous literature we attributed the reduced mobility to the broader distribution of the semiconductor density of states (DOS) due to a significant dipolar disorder in the dielectric layer. The combination of infrared (IR), solid-state nuclear magnetic resonance (NMR) and broadband dielectric (BDS) spectroscopy confirmed the presence of a rigid hydrogen bonds network in the CEPVA polymer. The formation of such network limits the dipolar disorder in the dielectric layer and leads to a significantly narrowed distribution of the density of states (DOS) and, hence, to the higher charge carrier mobility in the OFET active channel made of 6,13-bis(triisopropylsilylethynyl)pentacene. The low temperature drying process of CEPVA dielectric results in the decreased energy disorder of transport states in the adjacent semiconductor layer, which is then similar as in OFETs equipped with the much less polar poly(4-vinylphenol) (PVP). Breaking hydrogen bonds at temperatures around 50 °C results in the gradual disintegration of the stabilizing network and deterioration of the charge transport due to a broader distribution of DOS.

scholarly journals Current Tunnelling in MOS Devices with Al2O3/SiO2 Gate Dielectric

2008 ◽  
Vol 2008 ◽  
pp. 1-5 ◽  
Author(s):  
A. Bouazra ◽  
S. Abdi-Ben Nasrallah ◽  
M. Said ◽  
A. Poncet
Keyword(s):  
Dielectric Constant ◽  
Gate Dielectric ◽  
Oxide Thickness ◽  
Gate Leakage ◽  
Mos Devices ◽  
High K ◽  
Carrier Trap ◽  
High Dielectric ◽  
Very High ◽  
Tunnelling Current

With the continued scaling of the SiO2 thickness below 2 nm in CMOS devices, a large direct-tunnelling current flow between the gate electrode and silicon substrate is greatly impacting device performance. Therefore, higher dielectric constant materials are desirable for reducing the gate leakage while maintaining transistor performance for very thin dielectric layers. Despite its not very high dielectric constant (∼10), Al2O3 has emerged as one of the most promising high-k candidates in terms of its chemical and thermal stability as its high-barrier offset. In this paper, a theoretical study of the physical and electrical properties of Al2O3 gate dielectric is reported including I(V) and C(V) characteristics. By using a stack of Al2O3/SiO2 with an appropriate equivalent oxide thickness of gate dielectric MOS, the gate leakage exhibits an important decrease. The effect of carrier trap parameters (depth and width) at the Al2O3/SiO2 interface is also discussed.

Reduction of CV Hysteresis in Metal/High-k MISFETs Using Flash Lamp Post Deposition Annealing

2004 ◽  
Vol 811 ◽  
Author(s):  
Takeo Matsuki ◽  
Yasushi Akasaka ◽  
Kiyoshi Hayashi ◽  
Masataka Noguchi ◽  
Koji Yamashita ◽  
...  
Keyword(s):  
Charge Trapping ◽  
Gate Insulator ◽  
Flash Lamp ◽  
Gate Electrode ◽  
Post Deposition Annealing ◽  
Hysteresis Width ◽  
High K ◽  
Mis Capacitors ◽  
Hysteresis Characteristics ◽  
Post Deposition

ABSTRACTA Xe flash lamp (FL) heating technique was applied to the post deposition annealing process (PDA) for HfAlOx/SiO2 gate insulator with poly-Si or W/TiN gate electrode in a gate last based process. In the case of W/TiN/HfAlOx/SiO2, CV hysteresis with less than 10mV was achieved using the FL-PDA. However, the FL-PDA increased hysteresis width up to over 100 mV when poly-Si was used as a gate electrode. That occurred also with low temperature (700 °C) rapid thermal PDA process. The lower thermal budget achieved by the flash lamp annealing and the metal gate is effective to suppress the interfacial reaction which causes the traps responsible for the hysteresis. Charge trapping in the W/TiN/HfAlOx/SiO2 was evaluated using CV hysteresis characteristics in the MISFETs and the MIS capacitors. Electron was major trapped charge of the HfAlOx.

scholarly journals High-K dielectric sulfur-selenium alloys

2019 ◽  
Vol 5 (5) ◽  
pp. eaau9785 ◽  
Author(s):  
Sandhya Susarla ◽  
Thierry Tsafack ◽  
Peter Samora Owuor ◽  
Anand B. Puthirath ◽  
Jordan A. Hachtel ◽  
...  
Keyword(s):  
Dielectric Constant ◽  
Metal Oxides ◽  
High Dielectric Constant ◽  
Dielectric Material ◽  
Dielectric Strength ◽  
Dielectric Materials ◽  
High K ◽  
Device Applications ◽  
High K Dielectric ◽  
High Dielectric

Upcoming advancements in flexible technology require mechanically compliant dielectric materials. Current dielectrics have either high dielectric constant, K (e.g., metal oxides) or good flexibility (e.g., polymers). Here, we achieve a golden mean of these properties and obtain a lightweight, viscoelastic, high-K dielectric material by combining two nonpolar, brittle constituents, namely, sulfur (S) and selenium (Se). This S-Se alloy retains polymer-like mechanical flexibility along with a dielectric strength (40 kV/mm) and a high dielectric constant (K = 74 at 1 MHz) similar to those of established metal oxides. Our theoretical model suggests that the principal reason is the strong dipole moment generated due to the unique structural orientation between S and Se atoms. The S-Se alloys can bridge the chasm between mechanically soft and high-K dielectric materials toward several flexible device applications.

Alternate Gate Oxides for Silicon Mosfets Using High-k Dielectrics

1999 ◽  
Vol 567 ◽  
Author(s):  
C. A. Billman ◽  
P. H. Tan ◽  
K. J. Hubbard ◽  
D. G. Schlom
Keyword(s):  
Dielectric Constant ◽  
Thermodynamic Stability ◽  
Thermodynamic Data ◽  
Gate Dielectric ◽  
Inorganic Compounds ◽  
Gate Oxide ◽  
Gate Oxides ◽  
Binary Oxides ◽  
High K ◽  
Ranked List

ABSTRACTHigh K (dielectric constant) and silicon-compatibility are essential for an alternative gate dielectric for use in silicon MOSFETs. Thermodynamic data were used to comprehensively evaluate the thermodynamic stability of binary oxides and binary nitrides in contact with silicon at 1000 K. Using the Clausius-Mossotti equation and ionic polarizabilities, the K of all known inorganic compounds composed of Si-compatible binary oxides was estimated. A ranked list of alternate gate oxide candidates that are likely to possess both high K and silicon-compatibility is given.

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