Electrical modeling and simulation of nanoscale MOS devices with a high-permittivity dielectric gate stack

2004 ◽  
Vol 811 ◽  
Author(s):  
J.L. Autran ◽  
D. Munteanu ◽  
M. Houssa ◽  
M. Bescond ◽  
X. Garros ◽  
...  
Keyword(s):  
Mos Transistors ◽  
Gate Stack ◽  
Short Channel ◽  
Simulation Code ◽  
Fixed Charges ◽  
High K ◽  
Fringing Field ◽  
And Performance ◽  
High K Materials ◽  
High K Dielectric

ABSTRACTThe electrical behavior of decananometer MOS transistors with high-k dielectric gate stack has been investigated using 2D numerical simulation. Two important electrostatic limitations of high-k materials have been analyzed and discussed in this work: i) the gate-fringing field effects which compromise short-channel performance when simultaneously increasing the dielectric constant and its physical thickness and ii) the presence of discrete fixed charges in the gate stack, suspected to be at the origin of the stretch-out of C-V characteristics, that induces 2D potential fluctuations in the structure. In both cases, the resulting degradation of transistor operation and performance is evaluated with a two-dimensional quantum simulation code.

Effective Dielectric Thickness Scaling for High-K Gate Dielectric Mosfets

2002 ◽  
Vol 716 ◽  
Author(s):  
Krishna Kumar Bhuwalka ◽  
Nihar R. Mohapatra ◽  
Siva G. Narendra ◽  
V Ramgopal Rao
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Oxide Thickness ◽  
Channel Length ◽  
Short Channel ◽  
Dielectric Thickness ◽  
High K ◽  
Fringing Field ◽  
High K Dielectric ◽  
Physical Thickness

AbstractIt has been shown recently that the short channel performance worsens for high-K dielectric MOSFETs as the physical thickness to the channel length ratio increases, even when the effective oxide thickness (EOT) is kept identical to that of SiO2. In this work we have systematically evaluated the effective dielectric thickness for different Kgate to achieve targeted threshold voltage (Vt), drain-induced barrier lowering (DIBL) and Ion/Ioff ratio for different technology generations down to 50 nm using 2-Dimensional process and device simulations. Our results clearly show that the oxide thickness scaling for high-K gate dielectrics and SiO2 follow different trends and the fringing field effects must be taken into account for estimation of effective dielectric thickness when SiO2 is replaced by a high-K dielectric.

Channel hot-carrier degradation in pMOS and nMOS short channel transistors with high-k dielectric stack

2010 ◽  
Vol 87 (1) ◽  
pp. 47-50 ◽  
Author(s):  
E. Amat ◽  
T. Kauerauf ◽  
R. Degraeve ◽  
R. Rodríguez ◽  
M. Nafría ◽  
...  
Keyword(s):  
Short Channel ◽  
Hot Carrier ◽  
High K ◽  
High K Dielectric ◽  
Hot Carrier Degradation

Suppression of short channel effects in FinFETs using crystalline ZrO2 high-K/Al2O3 buffer layer gate stack for low power device applications

2018 ◽  
Vol 33 (3) ◽  
pp. 035013 ◽  
Author(s):  
Meng-Chen Tsai ◽  
Chin-I Wang ◽  
Yen-Chang Chen ◽  
Yi-Ju Chen ◽  
Kai-Shin Li ◽  
...  
Keyword(s):  
Low Power ◽  
Buffer Layer ◽  
Power Device ◽  
Short Channel Effects ◽  
Gate Stack ◽  
Short Channel ◽  
High K ◽  
Channel Effects ◽  
Device Applications

On the DIBL Reduction Effect of Short Channel Carbon Nanotube Field Effect Transistors

2016 ◽  
Vol 6 (4) ◽  
pp. 1514
Author(s):  
Khial Aicha ◽  
Rechem Djamil ◽  
Azizi Chrifa ◽  
Zaabat Mourad
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Liquid Nitrogen Temperature ◽  
Oxide Thickness ◽  
Short Channel ◽  
High K ◽  
Different Temperatures ◽  
Reduction Effect ◽  
High K Materials ◽  
Non Equilibrium Green’S Function

The Drain Induced Barrier Lowering (DIBL), in carbon Nanotubes-Fet (CNTFETS), is a challenging study that still needs investigation. Based on a numerical model, the Non-Equilibrium Green’s Function (NEGF) approach was applied to simulate the DIBL effect in CNTFETS. In this study,  the effect of the length gate ranging from 10 to 30 nm, for different temperatures (77K, 15K, 300K and 400K) on the DIBL was investigated. Then the variation of DIBL effect as a function of the nanotubes diameter varying over the following chiralities: (13, 0), (16, 0), (19, 0), (23, 0) and (25, 0) was undertaken. Afterworlds, we conducted the variation of DIBL impact as a function of the oxide thickness with the values: 1.5 nm, 3 nm, 4.5 nm, 6 nm and 7 nm. Moreover, the DIBL effect was carried at depending upon the high-k materials such as:  SiO_2, HfO_2, ZrO_2, 〖Ta〗_2 O_2 and TiO_2. Finally, a conclusion is made basing at the different findings which revealed that the best reduce of DIBL impact was recorded under a liquid Nitrogen temperature of 77 K.

Carrier transport mechanism in La-incorporated high-k dielectric/metal gate stack MOSFETs

2011 ◽  
Vol 88 (12) ◽  
pp. 3399-3403 ◽  
Author(s):  
Hyuk-Min Kwon ◽  
Won-Ho Choi ◽  
In-Shik Han ◽  
Min-Ki Na ◽  
Sang-Uk Park ◽  
...  
Keyword(s):  
Transport Mechanism ◽  
Carrier Transport ◽  
Metal Gate ◽  
Gate Stack ◽  
Carrier Transport Mechanism ◽  
High K ◽  
High K Dielectric

Simulation of the hot-carrier degradation in short channel transistors with high-K dielectric

2010 ◽  
Vol 23 (4-5) ◽  
pp. 315-323 ◽  
Author(s):  
E. Amat ◽  
T. Kauerauf ◽  
R. Degraeve ◽  
R. Rodríguez ◽  
M. Nafría ◽  
...  
Keyword(s):  
Short Channel ◽  
Hot Carrier ◽  
High K ◽  
High K Dielectric ◽  
Hot Carrier Degradation

Challenges in Integrating the High-K Gate Dielectric Film to the Conventional Cmos Process Flow

2001 ◽  
Vol 670 ◽  
Author(s):  
Avinash Agarwal ◽  
Michael Freiler ◽  
Pat Lysaght ◽  
Loyd Perrymore ◽  
Renate Bergmann ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Dielectric Film ◽  
Cmos Process ◽  
Gate Stack ◽  
Process Flow ◽  
High K ◽  
High K Materials ◽  
Wet Etch ◽  
The Impact ◽  
High K Gate Dielectric

ABSTRACTZrO2 and HfO2 and their alloys with SiO2 are currently among the leading high-k materials for replacing SiOxNy as the gate dielectric for the sub-100 nm technology nodes. International SEMATECH (ISMT) is currently investigating integration issues associated with this required change in materials. Our work has focused on the integration of ALCVD deposited ZrO2 and HfO2 with an industry standard conventional MOSFET process flow with poly-Si electrode. Since the impact of contamination by these new high-k materials introduced in a production fab has not yet been established, it becomes very critical to prevent cross- contamination through the process tools in the fab. A baseline study was completed within ISMT's fab and appropriate protocols for handling high-k materials have been established. The integrated high-k gate stack in a conventional transistor flow should not only meet all the performance requirements of scaled transistors, but the gate dielectric film should be able withstand high-temperature anneal steps. Reactions between ZrO2 and Si have been observed at temperatures as low as 560°C (during the amorphous Si deposition process). Various wet chemistries were also evaluated for removing the high-k film inadvertently deposited on wafer backside, and it was found that ZrO2 etches at extremely slow rates in the majority of the common wet etch chemistries available in a fab. A new hot HF based process was found to be successful in lowering Zr contamination on the wafer backside to as low as 1.8 E10 atoms/cm2. The patterning of a high-k gate stack with poly-Si electrode is another area that required considerable focus. Various dry (plasma) etch and wet etch chemistries were evaluated for etching ZrO2 using both blanket films as well as wafers with patterned poly-Si gate over the high-k films. On the full CMOS flow device wafers, most of these wet chemistries resulted in severe pitting in the ZrO2 film remaining over the source/drain (S/D) areas, as well as in the Si substrate and the field oxide. A poly-Si gate over ZrO2 gate dielectric film was successfully patterned using the standard poly-Si gate etch (Cl2/HBr) for the main etch, followed by a combination of HF and H2SO4 clean for removing all of the ZrO2 remaining over the S/D area. This allowed the fabrication of low-resistance contacts to transistor S/D areas, which ultimately resulted in demonstration of functional transistors with high-k gate dielectric films.

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