Effective Dielectric Thickness Scaling for High-K Gate Dielectric Mosfets

2002 ◽  
Vol 716 ◽  
Author(s):  
Krishna Kumar Bhuwalka ◽  
Nihar R. Mohapatra ◽  
Siva G. Narendra ◽  
V Ramgopal Rao
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Oxide Thickness ◽  
Channel Length ◽  
Short Channel ◽  
Dielectric Thickness ◽  
High K ◽  
Fringing Field ◽  
High K Dielectric ◽  
Physical Thickness

AbstractIt has been shown recently that the short channel performance worsens for high-K dielectric MOSFETs as the physical thickness to the channel length ratio increases, even when the effective oxide thickness (EOT) is kept identical to that of SiO2. In this work we have systematically evaluated the effective dielectric thickness for different Kgate to achieve targeted threshold voltage (Vt), drain-induced barrier lowering (DIBL) and Ion/Ioff ratio for different technology generations down to 50 nm using 2-Dimensional process and device simulations. Our results clearly show that the oxide thickness scaling for high-K gate dielectrics and SiO2 follow different trends and the fringing field effects must be taken into account for estimation of effective dielectric thickness when SiO2 is replaced by a high-K dielectric.

Effect of Technology Scaling on MOS Transistor Performance with High-K Gate Dielectrics

2002 ◽  
Vol 716 ◽  
Author(s):  
Nihar R. Mohapatra ◽  
Madhav P. Desai ◽  
Siva G. Narendra ◽  
V. Ramgopal Rao
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Channel Length ◽  
Mos Transistors ◽  
Short Channel ◽  
Technology Scaling ◽  
Mos Transistor ◽  
Wide Range ◽  
Impact Of Technology ◽  
The Impact

AbstractThe impact of technology scaling on the MOS transistor performance is studied over a wide range of dielectric permittivities using two-dimensional (2-D) device simulations. It is found that the device short channel performance is degraded with increase in the dielectric permittivity due to an increase in dielectric physical thickness to channel length ratio. For Kgate greater than Ksi, we observe a substantial coupling between source and drain regions through the gate dielectric. We provide extensive 2-D device simulation results to prove this point. Since much of the coupling between source and drain occurs through the gate dielectric, it is observed that the overlap length is an important parameter for optimizing DC performance in the short channel MOS transistors. The effect of stacked gate dielectric and spacer dielectric on the MOS transistor performance is also studied to substantiate the above observations.

Modeling and Designing a Device Using MuGFETs

2008 ◽  
Author(s):  
V. K. Lamba ◽  
Derick Engles ◽  
S. S. Malik
Keyword(s):  
Gate Dielectric ◽  
Silicon Film ◽  
General Rule ◽  
Channel Length ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Radius Of Curvature ◽  
Short Channel ◽  
Dielectric Thickness ◽  
Fin Thickness

This work describes computer simulations of various, Silicon on Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) with double and triple-gate structures, as well as gate-all-around devices. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. Here short-channel properties of multi-gate SOI MOSFETs (MuGFETs) are studied by numerical simulation. The evolution of characteristics such as Drain induced barrier lowering (DIBL), sub-threshold slope, and threshold voltage roll-off is analyzed as a function of channel length, silicon film or fin thickness, gate dielectric thickness and dielectric constant, and as a function of the radius of curvature of the corners. The notion of an equivalent gate number is introduced. As a general rule, increasing the equivalent gate number improves the short-channel behavior of the devices. Similarly, increasing the radius of curvature of the corners improves the control of the channel region by the gate.

scholarly journals Analog Performance of SOI nMuGFETs with Different TiN Gate Electrode Thickness and High-k Dielectrics

2011 ◽  
Vol 6 (2) ◽  
pp. 102-106
Author(s):  
Milene Galeti ◽  
Michele Rodrigues ◽  
Nadine Collaert ◽  
Eddy Simoen ◽  
Cor Claeys ◽  
...  
Keyword(s):  
Oxide Thickness ◽  
Voltage Gain ◽  
Gate Electrode ◽  
Metal Gate ◽  
Short Channel ◽  
High K ◽  
Analog Performance ◽  
Tin Metal ◽  
High K Dielectric ◽  
The Impact

This work presents an analysis of the analog performance of SOI MuGFET devices and the impact of different TiN metal gate electrode thickness.Thinner TiN metal gate allows achieving large gain and this effect can be attributed to the increased Early voltage values observed for thinner TiN metal gate. This VEA increase suggests an increase of the transversal electrical field for thin TiN metal gate (reduced gate oxide thickness) that is confirmed with the increment of the GIDL current.This impact on the voltage gain is maintained for short channel length.The impact of different gate dielectrics was also studied where high-k dielectric indicated a higher VT due to a VFB variation. Additionally, lower intrinsic voltage gain was observed for hafnium dielectric and this can be related to the lower Early voltage (VEA) present in this devices.

Effect of Device Parameters on Carbon Nanotube Field Effect Transistor in Nanometer Regime

2015 ◽  
Vol 36 ◽  
pp. 64-75 ◽  
Author(s):  
Sanjeet Kumar Sinha ◽  
Saurabh Chaudhury
Keyword(s):  
Threshold Voltage ◽  
Oxide Thickness ◽  
Channel Length ◽  
High Threshold ◽  
Length Variation ◽  
Chiral Vector ◽  
Metal Work Function ◽  
High K ◽  
High K Dielectric ◽  
Nanometer Regime

In this paper, we have analyzed the effect of chiral vector, temperature, metal work function, channel length and High-K dielectric on threshold voltage of CNTFET devices. We have also compared the effect of oxide thickness on gate capacitance and justified the advantage a CNTFET provides over MOSFET in nanometer regime. Simulation on HSPICE tool shows that high threshold voltage can be achieved at low chiral vector pair in CNTFET. It is also observed that the temperature has a negligible effect on threshold voltage of CNTFET. After that we have simulated and observed the effect of channel length variation on threshold voltage of CNTFET as well as MOSFET devices and given a theoretical analysis on it. We found an unusual, yet, favorable characteristics that the threshold voltage increases with decreasing channel length in CNTFET devices in deep nanometer regime.

Electrical modeling and simulation of nanoscale MOS devices with a high-permittivity dielectric gate stack

2004 ◽  
Vol 811 ◽  
Author(s):  
J.L. Autran ◽  
D. Munteanu ◽  
M. Houssa ◽  
M. Bescond ◽  
X. Garros ◽  
...  
Keyword(s):  
Mos Transistors ◽  
Gate Stack ◽  
Short Channel ◽  
Simulation Code ◽  
Fixed Charges ◽  
High K ◽  
Fringing Field ◽  
And Performance ◽  
High K Materials ◽  
High K Dielectric

ABSTRACTThe electrical behavior of decananometer MOS transistors with high-k dielectric gate stack has been investigated using 2D numerical simulation. Two important electrostatic limitations of high-k materials have been analyzed and discussed in this work: i) the gate-fringing field effects which compromise short-channel performance when simultaneously increasing the dielectric constant and its physical thickness and ii) the presence of discrete fixed charges in the gate stack, suspected to be at the origin of the stretch-out of C-V characteristics, that induces 2D potential fluctuations in the structure. In both cases, the resulting degradation of transistor operation and performance is evaluated with a two-dimensional quantum simulation code.

Influence of Channel Length and High-K Oxide Thickness on Subthreshold DC Performance of Graded Channel and Gate Stack DG-MOSFETs

NANO ◽  
2016 ◽  
Vol 11 (09) ◽  
pp. 1650101 ◽  
Author(s):  
Sarosij Adak ◽  
Sanjit Kumar Swain ◽  
Arka Dutta ◽  
Hafizur Rahaman ◽  
Chandan Kumar Sarkar
Keyword(s):  
High Speed ◽  
Oxide Thickness ◽  
Channel Length ◽  
Gate Stack ◽  
Short Channel ◽  
Power Circuit ◽  
Novel Device ◽  
High K ◽  
Channel Effects ◽  
High Speed Switching

Comparative assessment of graded channel gate stack (GCGS) DG MOSFET structure is done by using two-dimensional (2D) Sentrausu TCAD simulator for different high K oxide thickness. This novel device includes gate stack (GS) engineering (high K) and nonuniformly channel engineering (GC) to suppress the short channel effects and improve the device performance. This novel device can be a better alternative for the future high speed switching and low power circuit applications. It has the advantage of improved breakdown voltage, reduced leakage current, low output conductance and reduced bipolar parasitic effects. The given device must be properly investigated with respect to the variation of different high K oxide thickness on different parameters such as drain induced barrier lowering (DIBL), subthreshold slope (SS), [Formula: see text]/[Formula: see text], [Formula: see text] roll off before fabrication to have better reliability. The 2D Sentrausu TCAD simulator using drift-diffusion model was used to simulate the developed structure and good agreement is obtained with respect to already published result in the sub-threshold regime. The result indicates that there is a need to be optimize the DC parameters for specific circuit applications.

scholarly journals Performance of High-k Dielectric Material for Short Channel Length MOSFET Simulated using Silvaco TCAD Tools

2021 ◽  
Vol 19 (OCT2021) ◽  
pp. 143-148
Author(s):  
Fatin Antasha Anizam ◽  
Lyly Nyl Ismail ◽  
Norsabrina Sihab ◽  
Nur Sa’adah Mohd Sauki
Keyword(s):  
Dielectric Material ◽  
Channel Length ◽  
Short Channel ◽  
High K ◽  
High K Dielectric

Scalability of MOCVD-deposited Hafnium Oxide

2003 ◽  
Vol 765 ◽  
Author(s):  
S. Van Elshocht ◽  
R. Carter ◽  
M. Caymax ◽  
M. Claes ◽  
T. Conard ◽  
...  
Keyword(s):  
Hafnium Oxide ◽  
Interfacial Layer ◽  
Gate Dielectric ◽  
Deposition Process ◽  
Oxide Thickness ◽  
Process Conditions ◽  
Primary Concern ◽  
Gate Electrode ◽  
K Value ◽  
High K

AbstractBecause of aggressive downscaling to increase transistor performance, the physical thickness of the SiO2 gate dielectric is rapidly approaching the limit where it will only consist of a few atomic layers. As a consequence, this will result in very high leakage currents due to direct tunneling. To allow further scaling, materials with a k-value higher than SiO2 (“high-k materials”) are explored, such that the thickness of the dielectric can be increased without degrading performance.Based on our experimental results, we discuss the potential of MOCVD-deposited HfO2 to scale to (sub)-1-nm EOTs (Equivalent Oxide Thickness). A primary concern is the interfacial layer that is formed between the Si and the HfO2, during the MOCVD deposition process, for both H-passivated and SiO2-like starting surfaces. This interfacial layer will, because of its lower k-value, significantly contribute to the EOT and reduce the benefit of the high-k material. In addition, we have experienced serious issues integrating HfO2 with a polySi gate electrode at the top interface depending on the process conditions of polySi deposition and activation anneal used. Furthermore, we have determined, based on a thickness series, the k-value for HfO2 deposited at various temperatures and found that the k-value of the HfO2 depends upon the gate electrode deposited on top (polySi or TiN).Based on our observations, the combination of MOCVD HfO2 with a polySi gate electrode will not be able to scale below the 1-nm EOT marker. The use of a metal gate however, does show promise to scale down to very low EOT values.

scholarly journals Impact of device scaling on the electrical properties of MoS2 field-effect transistors

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Goutham Arutchelvan ◽  
Quentin Smets ◽  
Devin Verreck ◽  
Zubair Ahmed ◽  
Abhinav Gaur ◽  
...  
Keyword(s):  
Field Effect Transistors ◽  
Oxide Thickness ◽  
Channel Length ◽  
Contact Length ◽  
Power Performance ◽  
Semiconducting Materials ◽  
Large Area ◽  
Short Channel ◽  
Device Scaling ◽  
Performance Area

AbstractTwo-dimensional semiconducting materials are considered as ideal candidates for ultimate device scaling. However, a systematic study on the performance and variability impact of scaling the different device dimensions is still lacking. Here we investigate the scaling behavior across 1300 devices fabricated on large-area grown MoS2 material with channel length down to 30 nm, contact length down to 13 nm and capacitive effective oxide thickness (CET) down to 1.9 nm. These devices show best-in-class performance with transconductance of 185 μS/μm and a minimum subthreshold swing (SS) of 86 mV/dec. We find that scaling the top-contact length has no impact on the contact resistance and electrostatics of three monolayers MoS2 transistors, because edge injection is dominant. Further, we identify that SS degradation occurs at short channel length and can be mitigated by reducing the CET and lowering the Schottky barrier height. Finally, using a power performance area (PPA) analysis, we present a roadmap of material improvements to make 2D devices competitive with silicon gate-all-around devices.

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