Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture

2011 ◽  
Vol E94-C (10) ◽  
pp. 1669-1679 ◽  
Author(s):  
Shota ISHIHARA ◽  
Ryoto TSUCHIYA ◽  
Yoshiya KOMATSU ◽  
Masanori HARIYAMA ◽  
Michitaka KAMEYAMA
Keyword(s):  
Low Power ◽  
Hybrid Architecture

scholarly journals A Low Power Sigma-Delta Modulator with Hybrid Architecture

Sensors ◽  
2020 ◽  
Vol 20 (18) ◽  
pp. 5309
Author(s):  
Shengbiao An ◽  
Shuang Xia ◽  
Yue Ma ◽  
Arfan Ghani ◽  
Chan Hwang See ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Supply Voltage ◽  
Total Power ◽  
Cmos Process ◽  
Hybrid Architecture ◽  
Sigma Delta Modulator ◽  
Dynamic Comparator ◽  
Flash Adc ◽  
Total Power Consumption

Analogue-to-digital converters (ADC) using oversampling technology and the Σ-∆ modulation mechanism are widely applied in digital audio systems. This paper presents an audio modulator with high accuracy and low power consumption by using a discrete second-order feedforward structure. A 5-bit successive approximation register (SAR) quantizer is integrated into the chip, which reduces the number of comparators and the power consumption of the quantizer compared with flash ADC-type quantizers. An analogue passive adder is used to sum the input signals and it is embedded in a SAR ADC composed of a capacitor array and a dynamic comparator which has no static power consumption. To validate the design concept, the designed modulator is developed in a 180 nm CMOS process. The peak signal to noise distortion ratio (SNDR) is calculated as 106 dB and the total power consumption of the chip is recorded as 3.654 mW at the chip supply voltage of 1.8 V. The input sine wave of 0 to 25 kHz is sampled at a sampling frequency of 3.2 Ms/s. Moreover, the results achieve a 16-bit effective number of bits (ENOB) when the amplitude of the input signal is varied between 0.15 and 1.65 V. By comparing with other modulators which were realized by a 180 nm CMOS process, the proposed architecture outperforms with lower power consumption.

scholarly journals Memristor-Based Nonvolatile Random Access Memory: Hybrid Architecture for Low Power Compact Memory Design

IEEE Access ◽  
2013 ◽  
Vol 1 ◽  
pp. 29-34 ◽  
Author(s):  
Syed Shakib Sarwar ◽  
Syed An Nazmus Saqueb ◽  
Farhan Quaiyum ◽  
A. B. M. Harun-Ur Rashid
Keyword(s):  
Low Power ◽  
Random Access ◽  
Random Access Memory ◽  
Hybrid Architecture ◽  
Access Memory ◽  
Memory Design

scholarly journals Low Power, CMOS-MoS2 Memtransistor based Neuromorphic Hybrid Architecture for Wake-Up Systems

2019 ◽  
Vol 9 (1) ◽  
Author(s):  
Sarthak Gupta ◽  
Pratik Kumar ◽  
Tathagata Paul ◽  
André van Schaik ◽  
Arindam Ghosh ◽  
...  
Keyword(s):  
Low Power ◽  
High Performance ◽  
Building Blocks ◽  
Population Coding ◽  
Hybrid Architecture ◽  
Computationally Efficient ◽  
Molybdenum Disulphide ◽  
Process Technology ◽  
Ultra Low Power ◽  
Architectural Framework

Abstract Neuromorphic architectures have become essential building blocks for next-generation computational systems, where intelligence is embedded directly onto low power, small area, and computationally efficient hardware devices. In such devices, realization of neural algorithms requires storage of weights in digital memories, which is a bottleneck in terms of power and area. We hereby propose a biologically inspired low power, hybrid architectural framework for wake-up systems. This architecture utilizes our novel high-performance, ultra-low power molybdenum disulphide (MoS2) based two-dimensional synaptic memtransistor as an analogue memory. Furthermore, it exploits random device mismatches to implement the population coding scheme. Power consumption per CMOS neuron block was found to be 3 nw in the 65 nm process technology, while the energy consumption per cycle was 0.3 pJ for potentiation and 20 pJ for depression cycles of the synaptic device. The proposed framework was demonstrated for classification and regression tasks, using both off-chip and simplified on-chip sign-based learning techniques.

scholarly journals Development and Implementation of a Hybrid Wireless Sensor Network of Low Power and Long Range for Urban Environments

Sensors ◽  
2021 ◽  
Vol 21 (2) ◽  
pp. 567
Author(s):  
Juan Bravo-Arrabal ◽  
J. J. Fernandez-Lozano ◽  
Javier Serón ◽  
Jose Antonio Gomez-Ruiz ◽  
Alfonso García-Cerezo
Keyword(s):  
Wireless Sensor Network ◽  
Low Power ◽  
Urban Environment ◽  
Sensor Network ◽  
Long Range ◽  
Mobile Node ◽  
Urban Environments ◽  
Wireless Sensor ◽  
Hybrid Architecture ◽  
Web Mapping

The urban population, worldwide, is growing exponentially and with it the demand for information on pollution levels, vehicle traffic, or available parking, giving rise to citizens connected to their environment. This article presents an experimental long range (LoRa) and low power consumption network, with a combination of static and mobile wireless sensors (hybrid architecture) to tune and validate concentrator placement, to obtain a large coverage in an urban environment. A mobile node has been used, carrying a gateway and various sensors. The Activation By Personalization (ABP) mode has been used, justified for urban applications requiring multicasting. This allows to compare the coverage of each static gateway, being able to make practical decisions about its location. With this methodology, it has been possible to provide service to the city of Malaga, through a single concentrator node. The information acquired is synchronized in an external database, to monitor the data in real time, being able to geolocate the dataframes through web mapping services. This work presents the development and implementation of a hybrid wireless sensor network of long range and low power, configured and tuned to achieve efficient performance in a mid-size city, and tested in experiments in a real urban environment.

Ultra Low Power Bioelectronics

2009 ◽  
Author(s):  
Rahul Sarpeshkar
Keyword(s):  
Low Power ◽  
Ultra Low Power

Less Power, Greater Conflict

2018 ◽  
Vol 49 (1) ◽  
pp. 47-62 ◽  
Author(s):  
Petra C. Schmid
Keyword(s):  
Low Power ◽  
High Power ◽  
Goal Pursuit ◽  
Goal Conflict ◽  
Personal Goals ◽  
Multiple Goals ◽  
Objective Performance ◽  
The Future ◽  
The Way

Abstract. Power facilitates goal pursuit, but how does power affect the way people respond to conflict between their multiple goals? Our results showed that higher trait power was associated with reduced experience of conflict in scenarios describing multiple goals (Study 1) and between personal goals (Study 2). Moreover, manipulated low power increased individuals’ experience of goal conflict relative to high power and a control condition (Studies 3 and 4), with the consequence that they planned to invest less into the pursuit of their goals in the future. With its focus on multiple goals and individuals’ experiences during goal pursuit rather than objective performance, the present research uses new angles to examine power effects on goal pursuit.

An interdependence account of sexism and power: Men’s hostile sexism, biased perceptions of low power, and relationship aggression.

2019 ◽  
Vol 117 (2) ◽  
pp. 338-363 ◽  
Author(s):  
Emily J. Cross ◽  
Nickola C. Overall ◽  
Rachel S. T. Low ◽  
James K. McNulty
Keyword(s):  
Low Power ◽  
Hostile Sexism ◽  
Relationship Aggression

Power mad [low-power design]

2004 ◽  
Vol 18 (3) ◽  
pp. 37
Author(s):  
J. Frenkil
Keyword(s):  
Low Power ◽  
Low Power Design
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