scholarly journals PHYSICS OF MOSFET NANOTRANSISTORS: FUNDAMENTAL LIMITS AND RESTRICTIONS

2021 ◽  
Vol 18 (3) ◽  
pp. 4-28
Author(s):  
Yu. A. Kruglyak ◽  
M. V. Strikha

In the last one from the series of the tutorial review articles, devoted to physics of modern nanotransistors and aimed to serve reseachers, ingeneers, students and teachers in the universities, it is demonstrated that the existence of the minimal energy for recording of 1 bite of information leads to fundamental restriction on minimal MOSFET channel length and on minimal time of transistor swithching. The obtained simple estimation Lmin = 1.2 nm (for room temperature) is somewhat lower, than in reality, and it looks like that Si FETs with a channel shorter than 2.5–3 nm would newer be fabricated. This correlates with the results of numerical modeling of electron transport through the channel, which demonstrate that for short channels the greater part of current passes by tunneling below the barrier top, and the transistor loses its functionality, because the current in source-drain circuit is no longer governed by gate voltage.

Nanomaterials ◽  
2021 ◽  
Vol 11 (2) ◽  
pp. 329
Author(s):  
Wen Huang ◽  
Rui Zhang ◽  
Xuwen Xia ◽  
Parker Steichen ◽  
Nanjing Liu ◽  
...  

Zinc Oxide (ZnO) has been regarded as a promising electron transport layer (ETL) in perovskite solar cells (PSCs) owing to its high electron mobility. However, the acid-nonresistance of ZnO could destroy organic-inorganic hybrid halide perovskite such as methylammonium lead triiodide (MAPbI3) in PSCs, resulting in poor power conversion efficiency (PCE). It is demonstrated in this work that Nb2O5/ZnO films were deposited at room temperature with RF magnetron sputtering and were successfully used as double electron transport layers (DETL) in PSCs due to the energy band matching between Nb2O5 and MAPbI3 as well as ZnO. In addition, the insertion of Nb2O5 between ZnO and MAPbI3 facilitated the stability of the perovskite film. A systematic investigation of the ZnO deposition time on the PCE has been carried out. A deposition time of five minutes achieved a ZnO layer in the PSCs with the highest power conversion efficiency of up to 13.8%. This excellent photovoltaic property was caused by the excellent light absorption property of the high-quality perovskite film and a fast electron extraction at the perovskite/DETL interface.


Author(s):  
I.A. Tarasov ◽  
M.V. Rautskii ◽  
I.A. Yakovlev ◽  
M.N. Volochaev

AbstractSelf-assembled growth of α-FeSi_2 nanocrystal ensembles on gold-activated and gold-free Si(001) surface by molecular beam epitaxy is reported. The microstructure and basic orientation relationship (OR) between the silicide nanocrystals and silicon substrate were analysed. The study reveals that utilisation of the gold as catalyst regulates the preferable OR of the nanocrystals with silicon and their habitus. It is shown that electron transport from α-FeSi2 phase into p-Si(001) can be tuned by the formation of (001)—or (111)—textured α-FeSi2 nanocrystals ensembles. A current-voltage characteristic of the structures with different preferable epitaxial alignment (α-FeSi_2(001)/Si(100) and α-FeSi_2(111)/Si(100)) shows good linearity at room temperature. However, it becomes non-linear at different temperatures for different ORs due to different Schottky barrier height governed by a particular epitaxial alignment of the α-FeSi_2/ p -Si interfaces.


2014 ◽  
Vol 5 (1) ◽  
Author(s):  
Pradeep Bhadrachalam ◽  
Ramkumar Subramanian ◽  
Vishva Ray ◽  
Liang-Chieh Ma ◽  
Weichao Wang ◽  
...  

2013 ◽  
Vol 827 ◽  
pp. 282-286
Author(s):  
Gang Chen ◽  
Song Bai ◽  
Run Hua Huang ◽  
Yong Hong Tao ◽  
Ao Liu

SiC devices have excellent properties such as ultra low loss, high withstand voltage, large capacity, high frequency, and high temperature operation compared with Si devices. The SiC JFET is expected to be appropriate for the power device because a JFET has no oxide-semiconductor interface in the channel region and does not use the low mobility SiC MOSFET inversion layer as a channel. Forward I-V up to 4A for SiC VJFET, Gate voltage from 2V to 3.5V by step 0.5V. Reverse I-V characteristics up to 4500V (VG=-8V) for SiC VJFET, Gate voltage from-4V to-8V by step-2V. Turn-off characteristics are studied and fast turn-off time of 136ns at room temperature under DC voltage of 600V is successfully demonstrated.


Nano Letters ◽  
2014 ◽  
Vol 14 (2) ◽  
pp. 626-633 ◽  
Author(s):  
Arun V. Thathachary ◽  
Nidhi Agrawal ◽  
Lu Liu ◽  
Suman Datta

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