scholarly journals Improvement of Electrical Performance in P-Channel LTPS Thin-Film Transistor with a-Si:H Surface Passivation

2018 ◽  
Author(s):  
Kyungsoo Jang ◽  
Pham Duy Phong ◽  
Yoonjung Lee ◽  
Joonghyun Park ◽  
Junsin Yi
Keyword(s):  
Thin Film ◽  
High Performance ◽  
Surface Passivation ◽  
Thin Film Transistor ◽  
Passivation Layer ◽  
Electrical Performance ◽  
Electrical Characteristics ◽  
Silicon Thin Film ◽  
Hydrogen Dilution ◽  
Defect Sites

We report the effects of surface passivation by depositing a hydrogenated amorphous silicon (a-Si:H) layer on the electrical characteristics of low temperature polycrystalline silicon thin film transistors (LTPS TFTs). The a-Si:H layer was optimized by hydrogen dilution and its structural and electrical characteristics were investigated. The a-Si:H layer in the transition region between a-Si:H and µc-Si:H resulted in superior device characteristics. Using an a-Si:H passivation layer, the field-effect mobility of the LTPS TFT was increased by 78.4% compared with a conventional LTPS TFT. Moreover, the leakage current measured at a VGS of 5 V was suppressed because the defect sites at the poly-Si grain boundaries were well passivated. Our passivation layer, which allows thorough control of the crystallinity and passivation-quality, should be considered a candidate for high performance LTPS TFTs.

scholarly journals Improvement of Electrical Performance in P-Channel LTPS Thin-Film Transistor with a-Si:H Surface Passivation

Materials ◽  
2019 ◽  
Vol 12 (1) ◽  
pp. 161 ◽  
Author(s):  
Kyungsoo Jang ◽  
Youngkuk Kim ◽  
Pham Duy Phong ◽  
Younjung Lee ◽  
Joonghyun Park ◽  
...  
Keyword(s):  
Thin Film ◽  
High Performance ◽  
Surface Passivation ◽  
Thin Film Transistor ◽  
Passivation Layer ◽  
Electrical Performance ◽  
Electrical Characteristics ◽  
Silicon Thin Film ◽  
Hydrogen Dilution ◽  
Defect Sites

We report the effects of surface passivation by depositing a hydrogenated amorphous silicon (a-Si:H) layer on the electrical characteristics of low temperature polycrystalline silicon thin film transistors (LTPS TFTs). The intrinsic a-Si:H layer was optimized by hydrogen dilution and its structural and electrical characteristics were investigated. The a-Si:H layer in the transition region between a-Si:H and µc-Si:H resulted in superior device characteristics. Using a-Si:H passivation layer, the field-effect mobility of the LTPS TFT was increased by 78.4% compared with conventional LTPS TFT. Moreover, the leakage current measured at VGS of 5 V was suppressed because the defect sites at the poly-Si grain boundaries were well passivated. Our passivation layer, which allows thorough control of the crystallinity and passivation-quality, should be considered as a candidate for high performance LTPS TFTs.

scholarly journals Enhancement of electrical characteristics and stability of self-patterned In–Zn–O thin-film transistors based on photosensitive precursors

2020 ◽  
Vol 10 (1) ◽  
Author(s):  
Hee Jun Kim ◽  
Joohye Jung ◽  
Hyun Jae Kim
Keyword(s):  
Thin Film ◽  
Stress Test ◽  
Thin Film Transistor ◽  
Electrical Performance ◽  
Electrical Characteristics ◽  
Threshold Voltage Shift ◽  
Bias Stress ◽  
Indium Zinc Oxide ◽  
Defect Sites ◽  
Intrinsic Photosensitivity

Abstract We report a novel self-patterning method for solution-processed indium zinc oxide (IZO) thin films based on photosensitive precursors. This approach is an alternative and evolutionary approach to the traditional photoresist patterning techniques. Chelate bonds between metal ions and β-diketone compounds in ultraviolet light-exposed IZO solutions provided intrinsic photosensitivity, which resulted in a solubility difference between exposed and non-exposed regions. This difference enabled self-patterning of the IZO for thin-film transistor (TFT) fabrication. Compared with previously reported self-patterning methods based on photosensitive activators, our self-patterned IZO TFTs based on photosensitive precursors displayed excellent electrical characteristics and stability. The field-effect mobility increased from 0.27 to 0.99 cm2/Vs, the subthreshold swing decreased from 0.54 to 0.46 V/dec, and the threshold voltage shift under a positive bias stress test (1,000 s) improved from 9.32 to 1.68 V. The photosensitive precursor played a key role in these improvements permitting fewer organic species which act as defect sites after metal oxide formation. Consequently, our approach compares favorably with that of conventional fabrication process using photoresist in terms of its simplicity, cost efficiency, and electrical performance.

A High-Performance Polycrystalline Silicon Thin-Film Transistor Using Metal-Induced Crystallization with Ni Solution

1998 ◽  
Vol 37 (Part 1, No. 12B) ◽  
pp. 7193-7197 ◽  
Author(s):  
Soo Young Yoon ◽  
Sung Ki Kim ◽  
Jae Young Oh ◽  
YoungJin Choi ◽  
Woo Sung Shon ◽  
...  
Keyword(s):  
Thin Film ◽  
Polycrystalline Silicon ◽  
High Performance ◽  
Thin Film Transistor ◽  
Silicon Thin Film ◽  
Metal Induced Crystallization ◽  
Induced Crystallization

Device Characteristics of a Poly-Silicon Thin Film Transistor Fabricated by Milc at Low Temperature

1996 ◽  
Vol 424 ◽  
Author(s):  
Seok-Woon Lee ◽  
Byung-IL Lee ◽  
Tae-Hyung Ihn ◽  
Tae-Kyung Kim ◽  
Young-Tae Kang ◽  
...  
Keyword(s):  
Thin Film ◽  
High Performance ◽  
Solid Phase ◽  
Thin Film Transistor ◽  
Silicon Thin Film ◽  
Solid Phase Crystallization ◽  
Thin Nickel ◽  
One Step ◽  
Lateral Crystallization ◽  
Si Films

AbstractHigh performance poly-Si thin film transistors were fabricated by using a new crystallization method, Metal-Induced Lateral Crystallization (MILC). The process temperature was kept below 500°C throughout the fabrication. After the gate definition, thin nickel films were deposited on top of the TFT's without an additional mask, and with a one-step annealing at 500°C, the activation of the dopants in source/drain/gate a-Si films was achieved simultaneously with the crystallization of the a-Si films in the channel area. Even without a post-hydrogenation passivation, mobilities of the MILC TFT's were measured to be as high as 120cm2/Vs and 90cm2/Vs for n-channel and p-channel, respectively. These values are much higher than those of the poly-Si TFT's fabricated by conventional solid-phase crystallization at around 6001C.

A Novel Self-Aligned Field Induced Drain Polycrystalline Silicon Thin Film Transistor Fabricated by using a Selective Side Etch Process

2006 ◽  
Vol 910 ◽  
Author(s):  
Ta-Chuan Liao ◽  
Chun-Yu Wu ◽  
Feng-Tso Chien ◽  
Chun-Chien Tsai ◽  
Hsiu-Hsin Chen ◽  
...  
Keyword(s):  
Thin Film ◽  
Polycrystalline Silicon ◽  
Thin Film Transistor ◽  
Electrical Performance ◽  
Silicon Thin Film ◽  
Active Matrix ◽  
Light Emitting ◽  
Gate Structure ◽  
Vacuum Gaps ◽  
Matrix Liquid

AbstractA novel T-shaped-gated (T-Gate) polycrystalline silicon thin-film transistor (poly-Si TFT) with vacuum gaps has been proposed and fabricated only with a simple process. The T-Gate structure is formed only by a selective undercut-etching technology of the Mo/Al bi-layers. Then, vacuum gaps are in-situ embedded in this T-Gate structure subsequent to capping the SiH4-based passivation oxide under the vacuum process chamber. Experimental results reveal that the proposed T-Gate poly-Si TFTs have excellent electrical performance, which has higher maximum on-off current ratio of 4.6 e107, and the lower off-state leakage current at VGS = -10 V and VDS = 5V of about 100 times less than that of the conventional one. It is attributed to the additional undoped offset region and the vacuum gap to reduce the maximum electric field at drain junction while ascribed to the sub-gate to maintain the on-current. Therefore, such a T-Gate poly-Si TFT is very suitable for the applications and manufacturing in active matrix liquid crystal displays (AMLCDs) and active matrix organic light emitting diodes (AMOLEDs).

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