scholarly journals Power Efficient Model of PWM Generator for Green Computing and Communication on High Performance FPGAs

2021 ◽  
Author(s):  
Keshav Kumar ◽  
Bishwajeet Pandey
Keyword(s):  
High Performance ◽  
Average Power ◽  
Green Computing ◽  
Communication Model ◽  
Main Function ◽  
Green Communication ◽  
Power Efficient ◽  
Power And Energy ◽  
20 Nm ◽  
28 Nm

Abstract PWM generator is one of the core modules of a communication model. Its main function is to control the amplitude of signal and used for reducing average power of the pulses and signals. The PWM generator can also be used in promoting the green computing and green communication other than data and wireless communication if it is made power and energy efficient. In this work we are using different Stub Series Terminated Logic (SSTL) IO with three distinguished FPGAs of different Nano meter (nm) gate size that are 28 nm SPARTAN-7, 20 nm KINTEX-7 Ultra scale, and 16 nm ZYNQ Ultra scale+. The model has been synthesized and implemented on VIVADO ISE tool. From the power analysis it is observed that 16 nm ZYNQ Ultra scale+ requires the highest amount of power for operation with SSTL18_I IO and 28 nm SPARTAN-7 uses least amount of power for the operation with SSTL135 IO, while the 20 nm KINTEX-7 Ultra scale lies in mid of both of these devices.

POWER-EFFICIENT CONFIGURATION CACHE STRUCTURE FOR COARSE-GRAINED RECONFIGURABLE ARCHITECTURE

2013 ◽  
Vol 22 (03) ◽  
pp. 1350001 ◽  
Author(s):  
YOONJIN KIM
Keyword(s):  
High Performance ◽  
Average Power ◽  
Power Saving ◽  
Reducing Power ◽  
Coarse Grained ◽  
Context Management ◽  
Power Efficient ◽  
Processing Elements ◽  
Previous Design ◽  
Ip Cores

Coarse-grained reconfigurable architectures (CGRA) require many processing elements (PEs) and a configuration memory unit (configuration cache) for reconfiguration of its PE array. Although this structure is meant for high performance and flexibility, it consumes significant power. Specially, power consumption by configuration cache is explicit overhead compared to other types of IP cores. Reducing power in configuration cache is very crucial for CGRA to be more competitive and reliable processing core in embedded systems. In this paper, I propose a power-efficient configuration cache structure based on two design schemes — one is a reusable context pipelining (RCP) architecture to reduce power-overhead caused by reconfiguration and another is a dynamic context management strategy for power saving in configuration cache. This power-efficient approach works without degrading the performance and flexibility of CGRA. Experimental results show that the proposed approach saves 56.50%/86.84% of the average power in write/read-operation of configuration cache compared to the previous design.

scholarly journals Design of Energy Efficient Control Unit and Implementation on High Performance FPGA

2019 ◽  
Vol 8 (12S2) ◽  
pp. 23-26
Keyword(s):  
Power Consumption ◽  
Energy Efficient ◽  
Field Programmable Gate Array ◽  
High Performance ◽  
Control Unit ◽  
Input Output ◽  
Green Communication ◽  
Power Efficient ◽  
Efficient Control ◽  
Field Programmable

With the crisis of power across the globe, green communication and power-efficient devices are getting more and more attention. This work emphasis about the implementation of Control Unit (CU) circuit on FPGA kit. In this project, power consumption of CU circuit is analyzed by changing the different Input/Output (I/O) standards of FPGA. This project is implemented on Xilinx 14.1 tool and the power consumption on CU is calculated with X Power Analyzer tool on 28-Nano-Meter (nm) Artix-7 Field Programmable Gate Array (FPGA). Out of different I/O standards, CU circuit is most power efficient with LVCMOS I/O standard on Artix-7 FPGA

scholarly journals Design of Energy Efficient Control Unit and Implementation on High Performance FPGA

2019 ◽  
Vol 8 (12S2) ◽  
pp. 23-26
Keyword(s):  
Power Consumption ◽  
Energy Efficient ◽  
Field Programmable Gate Array ◽  
High Performance ◽  
Control Unit ◽  
Input Output ◽  
Green Communication ◽  
Power Efficient ◽  
Efficient Control ◽  
Field Programmable

With the crisis of power across the globe, green communication and power-efficient devices are getting more and more attention. This work emphasis about the implementation of Control Unit (CU) circuit on FPGA kit. In this project, power consumption of CU circuit is analyzed by changing the different Input/Output (I/O) standards of FPGA. This project is implemented on Xilinx 14.1 tool and the power consumption on CU is calculated with X Power Analyzer tool on 28-Nano-Meter (nm) Artix-7 Field Programmable Gate Array (FPGA). Out of different I/O standards, CU circuit is most power efficient with LVCMOS I/O standard on Artix-7 FPGA.

An E-learning System in Malaysia based on Green Computing and Energy Level

2017 ◽  
Vol 1 (4-2) ◽  
pp. 184 ◽  
Author(s):  
Arif Ullah ◽  
Nazri Mohd Nawi ◽  
Asim Shahzad ◽  
Sundas Naqeeb Khan ◽  
Muhammad Aamir
Keyword(s):  
Environmental Concern ◽  
Specific Area ◽  
Green Computing ◽  
Learning System ◽  
Main Step ◽  
Primary Concern ◽  
Green Is ◽  
E Learning ◽  
Energy Consuming ◽  
Power And Energy

The increasing of energy cost and also environmental concern on green computing gaining more and more attention. Power and energy are a primary concern in the design and implementing green computing. Green is of the main step to make the computing world friendly with the environment.  In this paper, an analysis on the comparison of green computer with other computing in E-learning environment had been done. The results show that green computing is friendly and less energy consuming. Therefore, this paper provide some suggestions in overcoming one of main challenging problems in environment problems which need to convert normally computing into green computing. In this paper also, we try to find out some specific area which consumes energy as compared to green computing in E –learning centre in Malaysia. The simulation results show that more than 30% of energy reduction by using green computing.

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

scholarly journals High performance, electroforming-free, thin film memristors using ionic Na0.5Bi0.5TiO3

2021 ◽  
Vol 9 (13) ◽  
pp. 4522-4531
Author(s):  
Chao Yun ◽  
Matthew Webb ◽  
Weiwei Li ◽  
Rui Wu ◽  
Ming Xiao ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Films ◽  
Resistive Switching ◽  
Growth Temperature ◽  
High Performance ◽  
20 Nm

Interfacial resistive switching and composition-tunable RLRS are realized in ionically conducting Na0.5Bi0.5TiO3 thin films, allowing optimised ON/OFF ratio (>104) to be achieved with low growth temperature (600 °C) and low thickness (<20 nm).

High performance continuously tunable top-emitting vertical cavity laser with 20 nm wavelength range

1997 ◽  
Vol 33 (12) ◽  
pp. 1051 ◽  
Author(s):  
M.Y. Li ◽  
W. Yuen ◽  
G.S. Li ◽  
C.J. Chang-Hasnain
Keyword(s):  
Wavelength Range ◽  
High Performance ◽  
Cavity Laser ◽  
20 Nm ◽  
Vertical Cavity

New RP-CVD grown ultra-high performance selectively B-doped pure-Ge 20 nm QWs on (100)Si as basis material for post-Si CMOS technology

2013 ◽  
Vol 11 (1) ◽  
pp. 61-64 ◽  
Author(s):  
O. A. Mironov ◽  
A. H. A. Hassan ◽  
M. Uhlarz ◽  
S. Kiatgamolchai ◽  
A. Dobbie ◽  
...  
Keyword(s):  
High Performance ◽  
Cmos Technology ◽  
Basis Material ◽  
20 Nm
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