scholarly journals Ge N-Channel MOSFETs with ZrO2 Dielectric Achieving the Improved Mobility

2021 ◽  
Author(s):  
Lulu Chou ◽  
Yan Liu ◽  
Yang Xu ◽  
Yue Peng ◽  
Huan Liu ◽  
...  
Keyword(s):  
Electron Mobility ◽  
Interfacial Layer ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
High Mobility ◽  
Gate Insulator ◽  
Equivalent Thickness ◽  
Effective Electron ◽  
Drive Current ◽  
Inversion Charge

Abstract High mobility Ge nMOSFETs with ZrO2 gate dielectric are demonstrated and compared against transistors with Al2O3/ZrO2 , ZrO2, and O3 /ZrO 2 gate dielectrics. The Al2O3/ZrO2 provides for dramatically enhanced-effective electron mobility ( μeff ), boosting transistor drive current. Ge nMOSFETs with the Al2O3 /ZrO2 gate insulator achieve a 50% μeff improvement as compared to the Si universal mobility at an inversion charge density ( Qinv ) of 5 × 10 12 cm -2 . An Al2O3 interfacial layer leads to a boost in μeff but increases capacitance equivalent thickness (CET). Utilizing O3 oxidation of Ge surface, Al2O3 -free Ge nMOSFETs having a CET of 1.1 nm obtains a peak μ eff of 682 cm2 /Vs, which is higher than that of the Si universal mobility at the similar Qinv .

scholarly journals Ge N-Channel MOSFETs with ZrO2 Dielectric Achieving Improved Mobility

2021 ◽  
Vol 16 (1) ◽  
Author(s):  
Lulu Chou ◽  
Yan Liu ◽  
Yang Xu ◽  
Yue Peng ◽  
Huan Liu ◽  
...  
Keyword(s):  
Charge Density ◽  
Electron Mobility ◽  
Interfacial Layer ◽  
High Performance ◽  
Gate Dielectric ◽  
High Mobility ◽  
Post Treatment ◽  
The Other ◽  
Effective Electron ◽  
Inversion Charge

AbstractHigh-mobility Ge nMOSFETs with ZrO2 gate dielectric are demonstrated and compared against transistors with different interfacial properties of ozone (O3) treatment, O3 post-treatment and without O3 treatment. It is found that with O3 treatment, the Ge nMOSFETs with ZrO2 dielectric having a EOT of 0.83 nm obtain a peak effective electron mobility (μeff) of 682 cm2/Vs, which is higher than that of the Si universal mobility at the medium inversion charge density (Qinv). On the other hand, the O3 post-treatment with Al2O3 interfacial layer can provide dramatically enhanced-μeff, achieving about 50% μeff improvement as compared to the Si universal mobility at medium Qinv of 5 × 1012 cm−2. These results indicate the potential utilization of ZrO2 dielectric in high-performance Ge nMOSFETs.

Effect of High Temperature Forming Gas Annealing on Electrical Properties of 4H-SiC Lateral MOSFETs with Lanthanum Silicate and ALD SiO2 Gate Dielectric

2018 ◽  
Vol 924 ◽  
pp. 482-485
Author(s):  
Min Seok Kang ◽  
Kevin Lawless ◽  
Bong Mook Lee ◽  
Veena Misra
Keyword(s):  
Threshold Voltage ◽  
Interfacial Layer ◽  
Field Effect ◽  
Lanthanum Oxide ◽  
Gate Dielectric ◽  
High Mobility ◽  
High Threshold ◽  
Field Effect Mobility ◽  
The Impact ◽  
Lanthanum Silicate

We investigated the impact of an initial lanthanum oxide (La2O3) thickness and forming gas annealing (FGA) conditions on the MOSFET performance. The FGA has been shown to dramatically improve the threshold voltage (VT) stability of 4H-SiC MOSFETs. The FGA process leads to low VTshift and high field effect mobility due to reduction of the interface states density as well as traps by passivating the dangling bonds and active traps in the Lanthanum Silicate dielectrics. By optimizing the La2O3interfacial layer thickness and FGA condition, SiC MOSFETs with high threshold voltage and high mobility while maintaining minimal VTshift are realized.

Study of SrTiO3 Gate Dielectrics

2006 ◽  
Vol 966 ◽  
Author(s):  
C.Y. Liu ◽  
Tseung-Yuen Tseng
Keyword(s):  
Dielectric Constant ◽  
Electrical Properties ◽  
Silicon Substrate ◽  
Interfacial Layer ◽  
High Dielectric Constant ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Measurement Techniques ◽  
High Quality ◽  
High Dielectric

ABSTRACTAmong various possible candidates of high-k gate dielectrics, SrTiO3 plays an important role because it has high dielectric constant and it can be epitaxially grown on silicon substrate. The fabrication process and properties of SrTiO3 gate dielectrics are reported. The effect of the addition of SiO2 on the microstructure and electrical properties of SrTiO3 gate dielectric is also presented. The minimization of the effect of interfacial layer between SrTiO3 and Si is the most important issue for obtaining high quality high-k gate dielectrics. The possible methods to improve the interfacial properties and the measurement techniques to characterize the interfacial layer are discussed.

High Channel Mobility of 4H-SiC MOSFETs Fabricated by Over-Oxidation of the N-/Al-Coimplanted Surface Layer

2009 ◽  
Vol 615-617 ◽  
pp. 765-768 ◽  
Author(s):  
Sergey A. Reshanov ◽  
Svetlana Beljakowa ◽  
Thomas Frank ◽  
Bernd Zippelius ◽  
Michael Krieger ◽  
...  
Keyword(s):  
Surface Layer ◽  
Threshold Voltage ◽  
Hall Mobility ◽  
Electron Mobility ◽  
Room Temperature ◽  
High Mobility ◽  
Interface Traps ◽  
Effective Electron ◽  
Channel Mobility ◽  
Positive Threshold

Conventional MOSFETs and Hall-bar MOSFETs are fabricated side by side by over-oxidation of N-implanted or N-/Al-coimplanted 4H-SiC layers. It is demonstrated that the N-/Al-coimplanted MOSFETs possess a positive threshold voltage at room temperature and reach high values of the channel mobility. The effective electron mobility and Hall mobility in Hall-bar MOSFETs are 31 cm2/Vs and 150 cm2/Vs, respectively, indicating a high density of interface traps in spite of the excellent high mobility values.

Fabrication of Organic Thin Film Transistors Using Low Temperature, Soluble Silicon Oxide as the Gate Dielectrics

2006 ◽  
Vol 965 ◽  
Author(s):  
Jeng-Hua Wei ◽  
HorngJiunn Lin ◽  
Ying-Ren Chen
Keyword(s):  
Thin Film ◽  
Silicon Oxide ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Thin Film Transistor ◽  
Gate Insulator ◽  
Breakdown Field ◽  
Organic Thin Film ◽  
Water Based ◽  
Low Threshold

ABSTRACTIn this paper, a unique water-based, liquid phase deposited silicon oxide (LPD SiO2) is adapted to the fabrication process of the organic thin film transistor (OTFT). Through the use of this process, an OTFT with a silicon oxide gate insulator is successfully fabricated at 100°C or less. At this low process temperature, the SiO2 functions efficiently as a gate dielectric with the breakdown field being larger than 5 MV/cm, the leakage current being near 1 pA/um2 with a gate bias of 20 V and the surface roughness being less than 1nm. Due to the high quality silicon oxide, the oxide-gated OTFT shows the low threshold voltage (-1 ∼ -2V) and medium on/off current ratio (∼1000). Because this oxide is a water-based process, it is highly resistant to the following soluble semiconductor material and its solvent.

High Mobility Pentacene Field Effect Transistors on Plastic

2005 ◽  
Vol 870 ◽  
Author(s):  
Siddharth Mohapatra ◽  
Michelle Grigas ◽  
Robert Wenz ◽  
Robert Rotzoll ◽  
Viorel Olariu ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Gate Dielectric ◽  
Field Effect Transistors ◽  
High Mobility ◽  
Channel Length ◽  
Surface Cleaning ◽  
Surface Treatments ◽  
Gate Insulator ◽  
Bottom Contact ◽  
Active Layers

AbstractThis paper reports the electrical properties of thin-film transistors with pentacene active layers used in a bottom contact transistor geometry utilizing solution processed poly-4-vinylphenol (PVP) as the gate dielectric processed on a polyethylene napthalate (PEN) substrate. The transistors sometimes exhibit mobilities in excess of 1cm2/Vs. The effect of various surface treatments of the gate insulator, on the electrical properties of these transistors discussed. The development of photolithographically defined 2νm channel length bottom contact transistors is emphasized as the speed of circuit elements such as the rectifier scale inversely as the square of the channel length of the transistors. Surface cleaning and semiconductor deposition techniques that improve transistor characteristics and reduce hysteresis are evaluated and the variation of the ION/IOFF ratios with the different surface treatments is noted.

AlON/SiO2 Stacked Gate Dielectrics for 4H-SiC MIS Devices

2009 ◽  
Vol 615-617 ◽  
pp. 541-544 ◽  
Author(s):  
Takuji Hosoi ◽  
Makoto Harada ◽  
Yusuke Kagei ◽  
Yuu Watanabe ◽  
Takayoshi Shimura ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Gate Insulator ◽  
Flat Band ◽  
Aluminum Oxynitride ◽  
Fixed Charges ◽  
Interface Charge ◽  
Capacitance Voltage ◽  
High Dielectric ◽  
Mis Devices

We propose the use of an aluminum oxynitride (AlON) gate insulator for 4H-SiC MIS devices. Since direct deposition of AlON on 4H-SiC substrate generates a large amount of interface charge due to an interfacial reaction, a thick AlON layer was deposited on underlying thin SiO2 thermally grown in N2O ambient. To reduce the negative fixed charge density in the aluminum oxide (Al2O3) film, we used reactive sputtering of Al in an N2/O2 gas mixture. The fabricated MIS capacitor with AlON/SiO2 stacked gate dielectric shows no flat band voltage shift and negligible capacitance-voltage hysteresis (30 mV), indicating the dielectric is almost free from both fixed charges and electrical defects. Owing to the high dielectric constant of AlON (k=6.9), as compared to single N2O-SiO2 gate insulator, significant gate leakage reduction was achieved by AlON/SiO2 stacked gate dielectrics even at high-temperature, especially in a high electric field condition (>5 MV/cm).

Scalability of MOCVD-deposited Hafnium Oxide

2003 ◽  
Vol 765 ◽  
Author(s):  
S. Van Elshocht ◽  
R. Carter ◽  
M. Caymax ◽  
M. Claes ◽  
T. Conard ◽  
...  
Keyword(s):  
Hafnium Oxide ◽  
Interfacial Layer ◽  
Gate Dielectric ◽  
Deposition Process ◽  
Oxide Thickness ◽  
Process Conditions ◽  
Primary Concern ◽  
Gate Electrode ◽  
K Value ◽  
High K

AbstractBecause of aggressive downscaling to increase transistor performance, the physical thickness of the SiO2 gate dielectric is rapidly approaching the limit where it will only consist of a few atomic layers. As a consequence, this will result in very high leakage currents due to direct tunneling. To allow further scaling, materials with a k-value higher than SiO2 (“high-k materials”) are explored, such that the thickness of the dielectric can be increased without degrading performance.Based on our experimental results, we discuss the potential of MOCVD-deposited HfO2 to scale to (sub)-1-nm EOTs (Equivalent Oxide Thickness). A primary concern is the interfacial layer that is formed between the Si and the HfO2, during the MOCVD deposition process, for both H-passivated and SiO2-like starting surfaces. This interfacial layer will, because of its lower k-value, significantly contribute to the EOT and reduce the benefit of the high-k material. In addition, we have experienced serious issues integrating HfO2 with a polySi gate electrode at the top interface depending on the process conditions of polySi deposition and activation anneal used. Furthermore, we have determined, based on a thickness series, the k-value for HfO2 deposited at various temperatures and found that the k-value of the HfO2 depends upon the gate electrode deposited on top (polySi or TiN).Based on our observations, the combination of MOCVD HfO2 with a polySi gate electrode will not be able to scale below the 1-nm EOT marker. The use of a metal gate however, does show promise to scale down to very low EOT values.

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