Effect of High Temperature Forming Gas Annealing on Electrical Properties of 4H-SiC Lateral MOSFETs with Lanthanum Silicate and ALD SiO2 Gate Dielectric

2018 ◽  
Vol 924 ◽  
pp. 482-485
Author(s):  
Min Seok Kang ◽  
Kevin Lawless ◽  
Bong Mook Lee ◽  
Veena Misra
Keyword(s):  
Threshold Voltage ◽  
Interfacial Layer ◽  
Field Effect ◽  
Lanthanum Oxide ◽  
Gate Dielectric ◽  
High Mobility ◽  
High Threshold ◽  
Field Effect Mobility ◽  
The Impact ◽  
Lanthanum Silicate

We investigated the impact of an initial lanthanum oxide (La2O3) thickness and forming gas annealing (FGA) conditions on the MOSFET performance. The FGA has been shown to dramatically improve the threshold voltage (VT) stability of 4H-SiC MOSFETs. The FGA process leads to low VTshift and high field effect mobility due to reduction of the interface states density as well as traps by passivating the dangling bonds and active traps in the Lanthanum Silicate dielectrics. By optimizing the La2O3interfacial layer thickness and FGA condition, SiC MOSFETs with high threshold voltage and high mobility while maintaining minimal VTshift are realized.

High Mobility 4H-SiC MOSFETs Using Lanthanum Silicate Interface Engineering and ALD Deposited SiO2

2014 ◽  
Vol 778-780 ◽  
pp. 557-561 ◽  
Author(s):  
Xiang Yu Yang ◽  
Bong Mook Lee ◽  
Veena Misra
Keyword(s):  
Threshold Voltage ◽  
Interfacial Layer ◽  
High Mobility ◽  
Atomic Layer ◽  
State Density ◽  
Silicate Layer ◽  
High Threshold ◽  
Interface Engineering ◽  
Dielectric Interface ◽  
Lanthanum Silicate

In this work, we have developed a novel gate stack to enhance the mobility of Si face (0001) 4H-SiC lateral MOSFETs while maintaining a high threshold voltage. The gate dielectric consists a thin lanthanum silicate layer at SiC/dielectric interface and SiO2deposited by atomic layer deposition. MOSFETs using this interface engineering technique show a peak field effect mobility of 133.5 cm2/Vs while maintaining a positive threshold voltage of above 3V. The interface state density measured on MOS capacitor with lanthanum silicate interfacial layers is reduced compared to the capacitors without the silicate. It is shown that the presence of the lanthanum at the interface reduces the formation of a lower quality SiOxinterfacial layer typically formed at the SiC surface during typical high temperature anneals. This better quality interfacial layer produces a sharp SiC/dielectric interface, which is confirmed by cross section Z-contrast STEM images.

Degradation of organic field-effect transistors made of pentacene

2004 ◽  
Vol 19 (7) ◽  
pp. 1999-2002 ◽  
Author(s):  
Ch. Pannemann ◽  
T. Diekmann ◽  
U. Hilleringmann
Keyword(s):  
Charge Carrier ◽  
Threshold Voltage ◽  
Field Effect ◽  
Gate Dielectric ◽  
Field Effect Transistors ◽  
Ambient Air ◽  
Organic Field Effect Transistors ◽  
Organic Thin Film ◽  
Field Effect Mobility ◽  
Semiconducting Material

This article reports degradation experiments on organic thin film transistors using the small organic molecule pentacene as the semiconducting material. Starting with degradation inert p-type silicon wafers as the substrate and SiO2 as the gate dielectric, we show the influence of temperature and exposure to ambient air on the charge carrier field-effect mobility, on-off-ratio, and threshold-voltage. The devices were found to have unambiguously degraded over 3 orders of magnitude in maximum on-current and charge carrier field-effect mobility, but they still operated after a period of 9 months in ambient air conditions. A thermal treatment was carried out in vacuum conditions and revealed a degradation of the charge carrier field-effect mobility, maximum on-current, and threshold voltage.

High field-effect mobility with suppressed negative threshold voltage shift in 4H-SiC MOSFET with cerium oxide interfacial layer

2021 ◽  
Vol 60 (3) ◽  
pp. 030901
Author(s):  
Jinhan Song ◽  
Atsuhiro Ohta ◽  
Takuya Hoshii ◽  
Hitoshi Wakabayashi ◽  
Kazuo Tsutsui ◽  
...  
Keyword(s):  
Cerium Oxide ◽  
Threshold Voltage ◽  
Interfacial Layer ◽  
Field Effect ◽  
High Field ◽  
Field Effect Mobility ◽  
Threshold Voltage Shift ◽  
Voltage Shift

Critical Issues for MOS Based Power Devices in 4H-SiC

2009 ◽  
Vol 615-617 ◽  
pp. 743-748 ◽  
Author(s):  
Sei Hyung Ryu ◽  
Sarit Dhar ◽  
Sarah K. Haney ◽  
Anant K. Agarwal ◽  
Aivars J. Lelis ◽  
...  
Keyword(s):  
Oxide Layer ◽  
Threshold Voltage ◽  
Field Effect ◽  
Gate Dielectric ◽  
Processing Technique ◽  
Field Effect Mobility ◽  
Power Devices ◽  
Thermal Oxide ◽  
Critical Issues ◽  
Operating Temperature Range

In this paper, we present the effects of MOS channel processing on the threshold voltage and the MOS field effect mobility of 4H-SiC MOSFETs. By increasing the p-well doping concentration by two orders of magnitude, the threshold voltage could be shifted positive from 0V to 5 V when a thermal oxide layer with NO post oxidation anneal was used as the gate dielectric layer. However, a severe degradation of MOS field effect mobility, decreasing from 37 cm2/Vs to 5 cm2/Vs, was also observed. Using a different processing technique, which uses a deposited oxide layer with an NO anneal, a threshold voltage of 7.5 V and a MOS field effect mobility of 15 cm2/Vs could be achieved. A 10 kV, 1 A power DMOSFET was demonstrated with this technique. A DMOSFET turn-off voltage of 5.25 V was measured at room temperature, which shifted to 3.0 V at 250oC, providing acceptable noise margins throughout the operating temperature range.

scholarly journals The impact of channel fin width on electrical characteristics of Si-FinFET

2022 ◽  
Vol 12 (1) ◽  
pp. 201
Author(s):  
Yousif Atalla ◽  
Yasir Hashim ◽  
Abdul Nasir Abd. Ghafar
Keyword(s):  
Threshold Voltage ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Environmental Temperature ◽  
Simulation Tool ◽  
Electrical Characteristics ◽  
Working Temperature ◽  
Effect Transistor ◽  
The Impact ◽  
The Ideal

<span>This paper studies the impact of fin width of channel on temperature and electrical characteristics of fin field-effect transistor (FinFET). The simulation tool multi-gate field effect transistor (MuGFET) has been used to examine the FinFET characteristics. Transfer characteristics with various temperatures and channel fin width (W<sub>F</sub>=5, 10, 20, 40, and 80 nm) are at first simulated in this study. The results show that the increasing of environmental temperature tends to increase threshold voltage, while the subthreshold swing (SS) and drain-induced barrier lowering (DIBL) rise with rising working temperature. Also, the threshold voltage decreases with increasing channel fin width of transistor, while the SS and DIBL increase with increasing channel fin width of transistor, at minimum channel fin width, the SS is very near to the best and ideal then its value grows and going far from the ideal value with increasing channel fin width. So, according to these conditions, the minimum value as possible of fin width is the preferable one for FinFET with better electrical characteristics.</span>

Thin Film Transistors on Plastic Substrates Using Silicon Deposited by Microwave ECR-CVD

2003 ◽  
Vol 769 ◽  
Author(s):  
Lihong Teng ◽  
Wayne A. Anderson
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Field Effect ◽  
Silicon Films ◽  
Subthreshold Swing ◽  
Field Effect Mobility ◽  
Current Ratio ◽  
Saturation Field ◽  
Plastic Substrates

AbstractThe properties of thin film transistors (TFT's) on plastic substrates with active silicon films deposited by microwave ECR-CVD were studied. Two types of plastic were used, PEEK and polyimide. The a-Si:H TFT deposited at 200°C on polyimide substrates showed a saturation field effect mobility of 4.5 cm2/V-s, a threshold voltage of 3.7 V, a subthreshold swing of 0.69 V/dec and an ON/OFF current ratio of 7.9×106, while the TFT fabricated on PEEK at 200°C showed a saturation field effect mobility of 3.9 cm2/V-s, a threshold voltage of 4.1 V, a subthreshold swing of 0.73 V/dec and an ON/OFF current ratio of 4×106. Comparison is made to TFT's with the Si deposited at 400°C on glass.

High Mobility a-Si:H TFT Fabricated by Hot Wire Chemical Vapor Deposition

2010 ◽  
Vol 1245 ◽  
Author(s):  
Chun-Yuan Hsueh ◽  
Chieh-Hung Yang ◽  
Si-Chen Lee
Keyword(s):  
Chemical Vapor Deposition ◽  
Vapor Deposition ◽  
Field Effect ◽  
High Mobility ◽  
Chemical Vapor ◽  
Field Effect Mobility ◽  
Hot Wire ◽  
Low Threshold ◽  
Hydrogenated Amorphous ◽  
Very High

AbstractThe hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs) having a very high field-effect mobility of 1.76 cm2/V-s and a low threshold voltage of 2.43 V have been fabricated successfully using the hot wire chemical vapor deposition (HWCVD).

Sign in / Sign up

Export Citation Format

Share Document