Highly Reliable Memory Operation of High Density Three-Terminal Thyristor Random Access Memory

Abstract Three-terminal (3-T) thyristor random-access memory is explored for a next generation high-density nanoscale vertical cross-point array. The effects of standby voltages on the device are thoroughly investigated in terms of gate-cathode voltage (VGC,ST) and anode- cathode voltage (VAC,ST) in the standby state for superior data retention characteristics and low-power operation. The device with the optimized VGC,ST of -0.4 V and VAC,ST of 0.55 V shows the continuous data retention capability without refresh operation with a low standby current of 0.13 pA. In addition, a memory array operation scheme of 3-T TRAM is proposed to address array disturbance issues. The presented array operation scheme can efficiently minimize program, erase and read disturbances on the adjacent unselected cells by adjusting gate-cathode voltage. The standby voltage turns out to be beneficial to improve retention characteristics: over 10 s. With the proposed memory array operation, 3-T TRAM can provide excellent data retention characteristics and high-density memory configurations comparable with or surpass conventional dynamic random-access memory (DRAM) technology.

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Highly Reliable Memory Operation of High Density Three-Terminal Thyristor Random Access Memory

10.21203/rs.3.rs-585213/v2 ◽

2021 ◽

Author(s):

Hyangwoo Kim ◽

Hyeonsu Cho ◽

Hyeon-Tak Kwak ◽

Myunghae Seo ◽

Seungho Lee ◽

...

Keyword(s):

Random Access ◽

Random Access Memory ◽

High Density ◽

Data Retention ◽

Access Memory ◽

Cathode Voltage ◽

Cross Point ◽

Memory Array ◽

Retention Characteristics ◽

Power Operation

Abstract Three-terminal (3-T) thyristor random-access memory is explored for a next generation high-density nanoscale vertical cross-point array. The effects of standby voltages on the device are thoroughly investigated in terms of gate-cathode voltage (VGC,ST) and anode- cathode voltage (VAC,ST) in the standby state for superior data retention characteristics and low-power operation. The device with the optimized VGC,ST of -0.4 V and VAC,ST of 0.6 V shows the continuous data retention capability without refresh operation with a low standby current of 1.14 pA. In addition, a memory array operation scheme of 3-T TRAM is proposed to address array disturbance issues. The presented array operation scheme can efficiently minimize program, erase and read disturbances on unselected cells by adjusting gate-cathode voltage. The standby voltage turns out to be beneficial to improve retention characteristics: over 10 s. With the proposed memory array operation, 3-T TRAM can provide excellent data retention characteristics and high-density memory configurations comparable with or surpass conventional dynamic random-access memory (DRAM) technology.

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Electrical and Data-Retention Characteristics of Two-Terminal Thyristor Random Access Memory

IEEE Open Journal of Nanotechnology ◽

10.1109/ojnano.2020.3042804 ◽

2020 ◽

Vol 1 ◽

pp. 163-169

Author(s):

Hyangwoo Kim ◽

Hyeonsu Cho ◽

Byoung Don Kong ◽

Jin-Woo Kim ◽

Meyya Meyyappan ◽

...

Keyword(s):

Random Access ◽

Random Access Memory ◽

Data Retention ◽

Access Memory ◽

Retention Characteristics

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Self-Compliance and High Performance Pt/HfOx/Ti RRAM Achieved through Annealing

Nanomaterials ◽

10.3390/nano10030457 ◽

2020 ◽

Vol 10 (3) ◽

pp. 457 ◽

Cited By ~ 4

Author(s):

Lei Wu ◽

Hongxia Liu ◽

Jinfu Lin ◽

Shulong Wang

Keyword(s):

Thermal Annealing ◽

High Performance ◽

Electrical Characteristic ◽

Random Access ◽

Random Access Memory ◽

Resistive Random Access Memory ◽

Data Retention ◽

Access Memory ◽

Before And After ◽

Retention Characteristics

A self-compliance resistive random access memory (RRAM) achieved through thermal annealing of a Pt/HfOx/Ti structure. The electrical characteristic measurements show that the forming voltage of the device annealing at 500 °C decreased, and the switching ratio and uniformity improved. Tests on the device’s cycling endurance and data retention characteristics found that the device had over 1000 erase/write endurance and over 105 s of lifetime (85 °C). The switching mechanisms of the devices before and after annealing were also discussed.

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The Influence of Water Absorbed in Grain Boundary of a Polycrystalline NiO Layer on the Memory Characteristics of Pt/NiO/Pt Resistive Random Access Memory (ReRAM)

MRS Proceedings ◽

10.1557/opl.2014.792 ◽

2014 ◽

Vol 1691 ◽

Cited By ~ 1

Author(s):

Ryosuke Ogata ◽

Masataka Yoshihara ◽

Naohiro Murayama ◽

Satoru Kishida ◽

Kentaro Kinoshita

Keyword(s):

Grain Boundary ◽

Room Temperature ◽

Random Access ◽

Random Access Memory ◽

Resistive Random Access Memory ◽

Data Retention ◽

Access Memory ◽

Influence Of Water ◽

Retention Characteristics ◽

Memory Characteristics

ABSTRACTWe focused on the presence of water absorbed in the grain boundary of a polycrystalline transition metal oxide (TMO) film in an EL/poly-TMO/EL structure. The effect of supplying water to resistive random access memories (ReRAMs) of Pt/NiO/Pt structure on switching voltages and data retention characteristics was investigated. As a result, switching voltages were decreased by supplying water and reset switching was confirmed to be strongly induced by supplying water even at room temperature without applying voltage. These results suggest that water enhances resistive switching effect by providing reducing species and oxidizing species respectively such as H+ and OH-.

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